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PDF PCF8532 Data sheet ( Hoja de datos )
| Número de pieza | PCF8532 | |
| Descripción | Universal LCD Driver | |
| Fabricantes | NXP Semiconductors | |
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PCF8532
Universal LCD driver for low multiplex rates
Rev. 1 — 10 February 2009
Product data sheet
1. General description
The PCF8532 is a peripheral device which interfaces to almost any Liquid Crystal Display
(LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed
LCD containing up to four backplanes and up to 160 segments and can easily be
cascaded for larger LCD applications. The PCF8532 is compatible with most
microprocessors or microcontrollers and communicates via a two-line bidirectional
I2C-bus. Communication overheads are minimized by a display RAM with
auto-incremental addressing, by hardware subaddressing and by display memory
switching (static and duplex drive modes).
2. Features
I Single-chip LCD controller and driver for up to 640 elements
I Selectable backplane drive configuration: static or 2, 3 or 4 backplane multiplexing
I 160 segment drives:
N Up to 80 7-segment numeric characters
N Up to 42 14-segment alphanumeric characters
N Any graphics of up to 640 elements
I May be cascaded for large LCD applications (up to 2560 elements possible)
I 160 × 4-bit RAM for display data storage
I Software programmable frame frequency in steps of 5 Hz in the range of 60 Hz to
90 Hz
I Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 8.0 V for
guest-host LCDs and high threshold (automobile) twisted nematic LCDs
I Internal LCD bias generation with voltage-follower buffers
I Selectable display bias configuration: static, 1⁄2 or 1⁄3
I Wide power supply range: from 1.8 V to 5.5 V
I LCD and logic supplies may be separated
I Low power consumption, typically: IDD = 4 µA, IDD(LCD) = 40 µA
I 400 kHz I2C-bus interface
I Auto-incremental display data loading across device subaddress boundaries
I Versatile blinking modes
I Compatible with Chip-On-Glass (COG) technology
I Display memory bank switching in static and duplex drive modes
I No external components
I Manufactured in silicon gate CMOS process
I Two sets of backplane outputs for optimal COG configurations of the application
1 page  
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PCF8532
Universal LCD driver for low multiplex rates
VDD
R
≤
tr
2CB
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDAACK
SDA
SCL
OSC
VDD VLCD
160 segment drives
PCF8532
4 backplanes
LCD PANEL
(up to 640
elements)
A0 A1 SA0 VSS
VSS
001aah852
Fig 3. Typical system configuration
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication
channel with the PCF8532.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to VSS. The only other connections required to complete the system are the
power supplies (VDD, VSS and VLCD) and the LCD panel selected for the application.
7.1 Power-on reset
At power-on the PCF8532 resets to a default starting condition:
• All backplane and segment outputs are set to VLCD
• The selected drive mode is 1:4 multiplex with 1⁄3 bias
• Blinking is switched off
• Input and output bank selectors are reset
• The I2C-bus interface is initialized
• The data pointer and the subaddress counter are cleared (set to logic 0)
• The display is disabled
• If internal oscillator is selected (OSC pin connected to VSS), then there is no clock
signal on pin CLK
Do not transfer data on the I2C-bus after a power-on for at least 1 ms to allow the reset
action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
series resistors connected between VLCD and VSS. The center resistor can be switched
out of the circuit to provide a 1⁄2 bias voltage level for the 1:2 multiplex configuration.
PCF8532_1
Product data sheet
Rev. 1 — 10 February 2009
© NXP B.V. 2009. All rights reserved.
5 of 44
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PCF8532
Universal LCD driver for low multiplex rates
7.4.3 1:3 multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as
shown in Figure 7.
BP0
BP1
BP2
Sn
Sn+1
Sn+2
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
VLCD / 3
VSS
state 1
state 2
VLCD
2VLCD / 3
VLCD / 3
0V
−VLCD / 3
−2VLCD / 3
−VLCD
VLCD
2VLCD / 3
VLCD / 3
0V
−VLCD / 3
−2VLCD / 3
−VLCD
Tfr
LCD segments
state 1
state 2
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
mgl748
Fig 7.
Vstate1(t) = VSn(t) − VBP0(t).
Von(RMS) = 0.638VLCD.
Vstate2(t) = VSn(t) − VBP1(t).
Voff(RMS) = 0.333VLCD.
Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
PCF8532_1
Product data sheet
Rev. 1 — 10 February 2009
© NXP B.V. 2009. All rights reserved.
11 of 44
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| PDF Descargar | [ Datasheet PCF8532.PDF ] | |
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