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Número de pieza | PCF8534A | |
Descripción | Universal LCD driver | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
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PCF8534A
Universal LCD driver for low multiplex rates
Rev. 00.90 — 4 February 2008
Product data sheet
1. General description
The PCF8534A is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD) with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 60 segments and can easily
be cascaded for larger LCD applications. The PCF8534A is compatible with most
microprocessors / microcontrollers and communicates via a two-line bidirectional I2C-bus.
Communication overheads are minimized using a display RAM with auto-incremented
addressing, hardware subaddressing and display memory switching (static and duplex
drive modes).
2. Features
Single-chip LCD controller / driver
Selectable backplane drive configuration: static or 2 / 3 / 4 backplane multiplexing
60 segment drives: up to thirty 8-segment numeric characters; up to sixteen
15-segment alphanumeric characters; or any graphics of up to 240 elements
May be cascaded for larger applications
60 × 4-bit RAM for display data storage
Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 6.5 V for
guest-host LCDs and high threshold (automobile) twisted nematic LCDs
Internal LCD bias generation with voltage-follower buffers
Selectable display bias configuration: static, 1⁄2 or 1⁄3
Wide logic power supply range: from 1.8 to 5.5 V
LCD and logic supplies may be separated
Low power consumption
400 kHz I2C-bus interface
Compatible with 4-bit, 8-bit or 16-bit microprocessors/microcontrollers
No external components
Display memory bank switching in static and duplex drive modes
Auto-incremented display data loading across device subaddress boundaries
Versatile blinking modes
TTL/CMOS compatible
Manufactured in silicon gate CMOS process
Automotive AEC-Q100 compliant.
1 page NXP Semiconductors
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PCF8534A
Universal LCD driver for low multiplex rates
Table 2.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin allocation table
Symbol
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
BP0
BP1
BP2
BP3
n.c.
n.c.
n.c.
n.c.
SDA
SCL
CLK
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PCF8534A_0
Product data sheet
Rev. 00.90 — 4 February 2008
Symbol
VDD
SYNC
OSC
A0
A1
A2
SA0
VSS
VLCD
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
© NXP B.V. 2008. All rights reserved.
5 of 41
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PCF8534A
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF8534A allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 6 and
Figure 7.
BP0
BP1
Sn
Sn+1
VLCD
VLCD/2
VSS
VLCD
VLCD/2
VSS
VLCD
VSS
VLCD
VSS
state 1
state 2
VLCD
VLCD/2
0V
−VLCD/2
−VLCD
VLCD
VLCD/2
0V
−VLCD/2
−VLCD
Tframe
LCD segments
state 1
state 2
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
mgl746
Fig 6.
Vstate1(t) = Vsn(t) − VBP0(t).
VON(rms) = 0.791 VLCD.
Vstate2(t) = V(sn)(t) − VBP1(t).
VOFF(rms) = 0.354 VLCD.
Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
PCF8534A_0
Product data sheet
Rev. 00.90 — 4 February 2008
© NXP B.V. 2008. All rights reserved.
11 of 41
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Páginas | Total 41 Páginas | |
PDF Descargar | [ Datasheet PCF8534A.PDF ] |
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