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ADAU1445 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADAU1445
Beschreibung (ADAU1445 / ADAU1446) Digital Audio Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADAU1445 Datasheet, Funktion
www.DataSheet4U.com
SigmaDSP Digital Audio Processor
with Flexible Audio Routing Matrix
ADAU1445/ADAU1446
FEATURES
Fully programmable audio digital signal processor (DSP) for
enhanced sound processing
Features SigmaStudio, a proprietary graphical programming
tool for the development of custom signal flows
172 MHz SigmaDSP core; 3584 instructions per sample at 48 kHz
4k parameter RAM, 8k data RAM
Flexible audio routing matrix (FARM)
24-channel digital input and output
Up to 8 stereo asynchronous sample rate converters
(from 1:8 up to 7.75:1 ratio and 139 dB DNR)
Stereo S/PDIF input and output
Supports serial and TDM I/O, up to fS = 192 kHz
Multichannel byte-addressable TDM serial port
Pool of 170 ms digital audio delay (at 48 kHz)
Clock oscillator for generating master clock from crystal
PLL for generating core clock from common audio clocks
I2C and SPI control interfaces
Standalone operation
Self-boot from serial EEPROM
4-channel, 10-bit auxiliary control ADC
Multipurpose pins for digital controls and outputs
Easy implementation of available third-party algorithms
On-chip regulator for generating 1.8 V from 3.3 V supply
100-lead TQFP and LQFP packages
Temperature range: −40°C to +105°C
APPLICATIONS
Automotive audio processing
Head units
Navigation systems
Rear-seat entertainment systems
DSP amplifiers (sound system amplifiers)
Commercial audio processing
FUNCTIONAL BLOCK DIAGRAM
MP[3:0]/
SPI/I2C* SELFBOOT MP[11:4] ADC[3:0]
XTALI XTALO
ADAU1445/
ADAU1446
1.8V
REGULATOR
I2C/SPI CONTROL
INTERFACE
AND SELF-BOOT
MP/
AUX ADC
CLOCK
PLL OSCILLATOR
CLKOUT
SPDIFI
S/PDIF
RECEIVER
PROGRAMMABLE AUDIO
PROCESSOR CORE
S/PDIF
TRANSMITTER
SPDIFO
SDATA_IN[8:0]
(24-CHANNEL
DIGITAL AUDIO
INPUT)
BIT CLOCK
(BCLK)
FRAME CLOCK
(LRCLK)
FLEXIBLE AUDIO ROUTING MATRIX
(FARM)
SERIAL DATA
INPUT PORT
(×9)
UP TO 16 CHANNELS OF
ASYNCHRONOUS
SAMPLE RATE
CONVERTERS
SERIAL DATA
OUTPUT PORT
(×9)
SERIAL CLOCK
DOMAINS
(×12)
SDATA_OUT[8:0]
(24-CHANNEL
DIGITAL AUDIO
OUTPUT)
BIT CLOCK
(BCLK)
FRAME CLOCK
(LRCLK)
*SPI/I2C = THE ADDR0, CLATCH, SCL/CCLK, SDA/COUT, AND ADDR1/CDATA PINS.
THERE ARE 12 BIT CLOCKS (BCLK[11:0]) AND 12 FRAME CLOCKS (LRCLK[11:0]) IN TOTAL. OF THE 12 CLOCKS,
SIX ARE ASSIGNABLE, THREE MUST BE OUTPUTS, AND THREE MUST BE INPUTS.
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.






ADAU1445 Datasheet, Funktion
wwAwD.DAatUaS1he4e4t45U./coAmDAU1446
DIGITAL TIMING SPECIFICATIONS
TA = −40°C to +105°C, DVDD = 1.8 V, IOVDD = 3.3 V.
Table 2.
Parameter1
MASTER CLOCK
fMP
tMP
tMD
CLKOUT Jitter
CORE CLOCK
fCORE
SERIAL PORT
fBCLK
tBCLK
tBIL
tBIH
tLIS
tLIH
tSIS
tSIH
tTS
tSODS
tSODM
SPI PORT
fCCLK write
fCCLK read
tCCPL
tCCPH
tCLS
tCLH
tCLPH
tCLDLY
tCDS
tCDH
tCOV
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tDH
tSCLR
tSCLF
tSDR
tSDF
tBFT
MULTIPURPOSE PINS AND RESET
fMP
tMPIL
Min
2.822
40.69
25
40.69
30
30
20
20
10
10
20
20
0
35
20
20
0
35
0.6
1.3
0.6
0.6
100
0.9
1.3
Max
24.576
354.36
75
250
172.032
24.576
5
30
30
32
16
40
400
300
300
300
300
fS/2
1.5 × 1/fS,NORMAL
tRLPW
10
Unit
MHz
ns
%
ps
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μs
μs
μs
μs
ns
μs
ns
ns
ns
ns
μs
Hz
μs
ns
Description
Master clock (MCLK) frequency. See the Master Clock and PLL section.
Master clock (MCLK) period. See the Master Clock and PLL section.
Master clock (MCLK) duty cycle.
Cycle-to-cycle rms average.
DSP core clock frequency.
BCLK frequency.
BCLK period.
BCLKx low pulse width, slave mode.
BCLKx high pulse width, slave mode.
LRCLKx setup to BCLKx input rising edge, slave mode.
LRCLKx hold from BCLKx input rising edge, slave mode.
SDATA_INx setup to BCLKx input rising edge.
SDATA_INx hold from BCLKx input rising edge.
BCLKx output falling edge to LRCLKx output timing skew.
SDATA_OUTx delay in slave mode from BCLKx output falling edge.
SDATA_OUTx delay in master mode from BCLKx output falling edge.
CCLK frequency.2
CCLK frequency.2
CCLK pulse width low.
CCLK pulse width high.
CLATCH setup to CCLK rising edge.
CLATCH hold from CCLK rising edge.
CLATCH pulse width high.
Minimum delay between CLATCH low pulses.
CDATA setup to CCLK rising edge.
CDATA hold from CCLK rising edge.
COUT valid output delay from CCLK falling edge.
SCL clock frequency.
SCL pulse width high.
SCL pulse width low.
Start and repeated start condition setup time.
Start condition hold time.
Data setup time.
Data hold time.
SCL rise time.
SCL fall time.
SDA rise time.
SDA fall time.
Bus-free time between stop and start.
MPx maximum switching rate.
MPx pin input latency until high/low value is read by core. Guaranteed by
design.
RESET low pulse width.
1 All timing specifications are given for the default (I2S) states of the serial audio input ports and the serial audio output ports (see Table 24 and Table 28).
2 Maximum SPI CCLK clock frequency is dependent on current drive strength and capacitive loads on the circuit board.
Rev. A | Page 6 of 92

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ADAU1445 pdf, datenblatt
wwAwD.DAatUaS1he4e4t45U./coAmDAU1446
Pin No.
34
35
36
40
41
42
43
44
45
46
47
48
49
53
54
55
56
57
58
59
60
61
64
65
Mnemonic
MP6
MP5
MP4
VDRIVE
XTALO
XTALI
PLL_FILT
PVDD
PGND
SPDIFI
SPDIFO
AVDD
AGND
CLKOUT
RESET
MP3/ADC3
MP2/ADC2
MP1/ADC1
MP0/ADC0
PLL1
PLL0
SDATA_OUT8
BCLK11
LRCLK11
Type1
D_IO
D_IO
D_IO
A_OUT
A_OUT
A_IN
A_OUT
PWR
PWR
D_IN
D_OUT
PWR
PWR
D_OUT
D_IN
D_IO,
A_IN
D_IO,
A_IN
D_IO,
A_IN
D_IO,
A_IN
D_IN
D_IN
D_OUT
D_IO
D_IO
Description
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
Regulator Drive. Supplies the drive current for the 1.8 V regulator. The base of the voltage regulator’s
external PNP transistor is driven from VDRIVE.
Crystal Oscillator Output. A 100 Ω damping resistor should be connected between this pin and the
crystal. This output should not be used to directly drive a clock to another IC; the CLKOUT pin
exists for this purpose. If the crystal oscillator is not used, the XTALO pin can be left unconnected.
Crystal Oscillator Input. This pin provides the master clock for the ADAU1445/ADAU1446. If the
ADAU1445/ADAU1446 generate the master clock in the system, this pin should be connected to
the crystal oscillator circuit. If the ADAU1445/ADAU1446 are slaves to an external master clock, this
pin should be connected to the master clock signal generated by another IC.
Phase-Locked Loop Filter. Two capacitors and a resistor must be connected to this pin as shown in
Figure 11.
Phase-Locked Loop Supply. Provides the 3.3 V power supply for the PLL. This should be decoupled
to PGND with a100 nF capacitor.
Phase-Locked Loop Ground. Ground for the PLL supply. The AGND, DGND, and PGND pins can be
tied directly together in a common ground plane. PGND should be decoupled to PVDD with a
100 nF capacitor.
S/PDIF Input. Accepts digital audio data in the S/PDIF format. When not used, this pin can be left
disconnected.
S/PDIF Output. Outputs digital audio data in the S/PDIF format. When not used, this pin can be left
disconnected.
Analog Supply. 3.3 V analog supply for the auxiliary ADC. This pin should be decoupled to AGND
with a 100 nF capacitor.
Analog Ground. Ground for the analog supply. This pin should be decoupled to AVDD with a
100 nF capacitor.
Master Clock Output. Used to output a master clock to other ICs in the system. Set using the
CLKMODEx pins. When not used, this pin can be left disconnected.
Reset. Active-low reset input. Reset is triggered on a high-to-low edge and exited on a low-to-high
edge. For detailed information about initialization, see the Power-Up Sequence section. A reset
event sets all RAMs and registers to their default values.
Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 3. When not used, this pin can
be left disconnected.
Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 2. When not used, this pin can
be left disconnected.
Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 1. When not used, this pin can
be left disconnected.
Multipurpose, General-Purpose IO/Auxiliary ADC Input 0. When not used, this pin can be left
disconnected.
Phase-Locked Loop Mode Select Pin 1.
Phase-Locked Loop Mode Select Pin 0.
Serial Data Port 0 Output. When not used, this pin can be left disconnected.
Bit Clock, Output Clock Domain 2. This pin is bidirectional, with the direction depending on whether the
Output Clock Domain 2 is set up as a master or slave. When not used, this pin can be left disconnected.
Frame Clock, Output Clock Domain 2. This pin is bidirectional, with the direction depending on
whether the Output Clock Domain 2 is set up as a master or slave. When not used, this pin can be
left disconnected.
Rev. A | Page 12 of 92

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