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PDF AD8275 Data sheet ( Hoja de datos )
| Número de pieza | AD8275 | |
| Descripción | 16-Bit ADC Driver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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1. AD8275  Hay una vista previa y un enlace de descarga de AD8275 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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FEATURES
Translates ±10 V to +4 V
Drives 16-bit SAR ADCs
Small MSOP package
Input overvoltage: +40 V to −35 V (VS = 5 V)
Fast settling time: 450 ns to 0.001%
Rail-to-rail output
Wide supply operation: +3.3 V to +15 V
High CMRR: 80 dB
Low gain drift: 1 ppm/°C
Low offset drift: 2.5 μV/°C
APPLICATIONS
Level translator
ADC driver
Instrumentation amplifier building block
Automated test equipment
GENERAL DESCRIPTION
The AD8275 is a G = 0.2 difference amplifier that can be used
to translate ±10 V signals to a +4 V level. It solves the problem
typically encountered in industrial and instrumentation applic-
ations where ±10 V signals must be interfaced to a single-supply
4 V or 5 V ADC. The AD8275 interfaces the two signal levels,
simplifying design.
The AD8275 has fast settling time of 450 ns and low distortion,
making it suitable for driving medium speed successive approx-
imation (SAR) ADCs. Its wide input voltage range and rail-to-
rail outputs make it an easy to use building block. Single-supply
operation reduces the power consumption of the amplifier and
helps to protect the ADC from overdrive conditions.
Internal, matched, precision laser-trimmed resistors ensure
low gain error, low gain drift of 1 ppm/°C (maximum), and
high common-mode rejection of 80 dB. Low offset and low
offset drift, combined with its fast settling time, make the
AD8275 suitable for a variety of data acquisition applications
where accurate and quick capture is required.
G = 0.2, Level Translation,
16-Bit ADC Driver
AD8275
+10V
–10V VIN
PIN CONFIGURATION
REF1 1
–IN 2
+IN 3
–VS 4
AD8275
TOP VIEW
(Not to Scale)
8 REF2
7 +VS
6 OUT
5 SENSE
Figure 1.
TYPICAL APPLICATION
+5V
0.1µF
0.1µF
50kΩ
2
–IN
7
+VS
10kΩ
5
SENSE
OUT
6
50kΩ
3
+IN
20kΩ
8
REF2
20kΩ
1
REF1
AD8275 –VS
4
+4.048V
+2.048V
+0.048V
33Ω
2.7nF
VDD
IN+
AD7685
IN–
REF
GND
VREF
4.096V
10µF
Figure 2. Translating ±10 V to 4.096 V ADC Full Scale
The AD8275 can be used as an analog front end, or it can follow
buffers to level translate high voltages to a voltage range accepted
by the ADC. In addition, the AD8275 can be configured for diff-
erential outputs if used with a differential ADC.
The AD8275 is available in a space-saving, 8-lead MSOP
and is specified for performance over the −40°C to +85°C
temperature range.
Table 1. Difference Amplifiers by Category
Low Distortion
High Voltage
Single-Supply
Current Sense
AD8270
AD628
AD8202
AD8273
AD629
AD8203
AD8274
AD8205
AD8275
AD8206
AMP03
AD8216
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008-2010 Analog Devices, Inc. All rights reserved.
1 page  
AD8275
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Output Short-Circuit Current
Voltage at +IN, −IN Pins
Voltage at REFx, +VS, − VS, SENSE,
and OUT Pins
Current into REFx, +IN, −IN, SENSE,
and OUT Pins
Storage Temperature Range
Specified Temperature Range
Thermal Resistance (θJA)
Package Glass Transition Temperature
(TG)
ESD Human Body Model
Rating
18 V
See derating curve
(Figure 3)
−VS + 40 V, +VS − 40 V
−VS − 0.5 V, +VS + 0.5 V
3 mA
−65°C to +130°C
−40°C to +85°C
135°C/W
140°C
2 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8275 package is
limited by the associated rise in junction temperature (TJ) on
the die. The plastic encapsulating the die locally reaches the
junction temperature. At approximately 140°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8275. Exceeding
a junction temperature of 140°C for an extended period can
result in changes in silicon devices, potentially causing failure.
The still air thermal properties of the package and PCB (θJA),
the ambient temperature (TA), and the total power dissipated in
the package (PD) determine the junction temperature of the die.
The junction temperature is calculated as follows:
TJ = TA + (PD × θJA)
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, the total drive power is VS/2 × IOUT, some of which is
dissipated in the package and some of which is dissipated in the
load (VOUT × IOUT).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
PD = Quiescent Power + (Total Drive Power − Load Power)
( )PD = VS × I S
+
VS
2
×
VOUT
RL
–
VOUT 2
RL
In single-supply operation with RL referenced to –VS, the worst
case is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature on a 4-layer JEDEC
standard board.
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
–40 –20
0 20 40 60 80
AMBIENT TEMPERATURE (°C)
100 120
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. A | Page 4 of 16
5 Page 
AD8275
10V/DIV
10mV/DIV
2µs/DIV
Figure 29. Large Signal Pulse Response and Settling Time, RL = 2 kΩ
1.0
VOUT = 4V p-p
0.1
0.01
RL = 600Ω
0.001
RL = 2kΩ
RL = 10kΩ
0.0001
10
100 1k 10k
FREQUENCY (Hz)
Figure 30. THD + N vs. Frequency, VOUT = 4 V p-p
100k
Rev. A | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AD8275.PDF ] | |
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