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PCA9674A Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCA9674A
Beschreibung Remote 8-bit I/O expander
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCA9674A Datasheet, Funktion
www.DataSheet4U.com
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
Rev. 02 — 12 October 2006
Product data sheet
1. General description
The PCA9674/74A provide general purpose remote I/O expansion for most
microcontroller families via the two-line bidirectional bus (I2C-bus) and is a part of the
Fast-mode Plus (Fm+) family.
The PCA9674/74A is a drop-in upgrade for the PCF8574/74A providing higher Fast-mode
Plus I2C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWM
dimming of LEDs, higher I2C-bus drive (30 mA versus 3 mA) so that many more devices
can be on the bus without the need for bus buffers, higher total package sink capacity
(200 mA versus 100 mA) that supports having all LEDs on at the same time and more
device addresses (64 versus 8) are available to allow many more devices on the bus
without address conflicts.
The devices consist of an 8-bit quasi-bidirectional port and an I2C-bus interface. The
PCA9674/74A have low current consumption and include latched outputs with 25 mA high
current drive capability for directly driving LEDs.
They also possess an interrupt line (INT) that can be connected to the interrupt logic of
the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform
the microcontroller if there is incoming data on its ports without having to communicate via
the I2C-bus.
The internal Power-On Reset (POR) or Software Reset sequence initializes the I/Os as
inputs.
2. Features
I 1 MHz I2C-bus interface
I Compliant with the I2C-bus Fast and Standard modes
I SDA with 30 mA sink capability for 4000 pF buses
I 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
I 8-bit remote I/O pins that default to inputs at power-up
I Latched outputs with 25 mA sink capability for directly driving LEDs
I Total package sink capability of 200 mA
I Active LOW open-drain interrupt output
I 64 programmable slave addresses using 3 address pins
I Readable device ID (manufacturer, device type, and revision)
I Low standby current
I 40 °C to +85 °C operation
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101






PCA9674A Datasheet, Funktion
www.DNatXaSPheSete4Um.coicmonductors
PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
Table 4.
Symbol
AD2
P0
P1
P2
P3
VSS[1]
P4
P5
P6
P7
INT
SCL
SDA
VDD
AD0
AD1
Pin description for HVQFN16
Pin Description
1 address input 2
2 quasi-bidirectional I/O 0
3 quasi-bidirectional I/O 1
4 quasi-bidirectional I/O 2
5 quasi-bidirectional I/O 3
6 supply ground
7 quasi-bidirectional I/O 4
8 quasi-bidirectional I/O 5
9 quasi-bidirectional I/O 6
10 quasi-bidirectional I/O 7
11 interrupt output (active LOW)
12 serial clock line
13 serial data line
14 supply voltage
15 address input 0
16 address input 1
[1] HVQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
7. Functional description
Refer to Figure 1 “Block diagram of PCA9674/74A”.
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9674/74A is shown in Figure 8. Slave address pins AD2, AD1, and AD0 choose 1 of
64 slave addresses. To conserve power, no internal pull-up resistors are incorporated on
AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in
Table 5 “PCA9674 address map” and Table 6 “PCA9674A address map”.
Remark: When using the PCA9674A, the General Call address (0000 0000b) and the
Device ID address (1111 100Xb) are reserved and cannot be used as device address.
Failure to follow this requirement will cause the PCA9674A not to acknowledge.
Remark: When using the PCA9674 or the PCA9674A, reserved I2C-bus addresses must
be used with caution since they can interfere with:
“reserved for future use” I2C-bus addresses (0000 011, 1111 101, 1111 110,
1111 111)
slave devices that use the 10-bit addressing scheme (1111 0xx)
High speed mode (Hs-mode) master code (0000 1xx)
PCA9674_PCA9674A_2
Product data sheet
Rev. 02 — 12 October 2006
© NXP B.V. 2006. All rights reserved.
6 of 34

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PCA9674A pdf, datenblatt
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PCA9674/74A
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt
7.2.2 Device ID (PCA9674/74A ID field)
The Device ID field is a 3-byte read-only (24 bits) word giving the following information:
8 bits with the manufacturer name, unique per manufacturer (for example, NXP).
13 bits with the part identification, assigned by manufacturer, the 7 MSBs with the
category ID and the 6 LSBs with the feature ID (for example, for example
PCA9674/74A 16-bit quasi-output I/O expander).
3 bits with the die revision, assigned by manufacturer (for example, Rev X).
The Device ID is read-only, hardwired in the device and can be accessed as follows:
1. START command
2. The master sends the Reserved Device ID I2C-bus address ‘1111 100’ with the R/W
bit set to 0 (write).
3. The master sends the I2C-bus slave address of the slave device it needs to identify.
The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one
that has the I2C-bus slave address).
4. The master sends a Re-START command.
Remark: A STOP command followed by a START command will reset the slave state
machine and the Device ID read cannot be performed.
Remark: A STOP command or a Re-START command followed by an access to
another slave device will reset the slave state machine and the Device ID read cannot
be performed.
5. The master sends the Reserved Device ID I2C-bus address ‘1111 100’ with the R/W
bit set to 1 (read).
6. The device ID read can be done, starting with the 8 manufacturer bits (first byte +
4 MSB of the second byte), followed by the 13 part identification bits and then the
3 die revision bits (3 LSB of the third byte).
7. The master ends the reading sequence by NACKing the last byte, thus resetting the
slave device state machine and allowing the master to send the STOP command.
Remark: The reading of the Device ID can be stopped anytime by sending a NACK
command.
Remark: If the master continues to ACK the bytes after the third byte, the
PCA9674/74A rolls back to the first byte and keeps sending the Device ID sequence
until a NACK has been detected.
For the PCA9674/74A, the Device ID is as shown in Figure 12.
PCA9674_PCA9674A_2
Product data sheet
manufacturer 0 0 0 0 0 0 0 0
part identification 0 0 0 0 0 0 1 0 0 1 0 1 1
category identification
feature identification
revision 0 0 0
002aac118
Fig 12. PCA9674/74A ID
Rev. 02 — 12 October 2006
© NXP B.V. 2006. All rights reserved.
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