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PDF DS4426 Data sheet ( Hoja de datos )
| Número de pieza | DS4426 | |
| Descripción | I��C-Margining IDACs | |
| Fabricantes | Maxim Integrated Products　 | |
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19-4541; Rev 0; 4/09
www.DataSheet4U.com
Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
General Description
The DS4426 contains four I2C-adjustable current DACs
capable of sinking or sourcing current. External resis-
tors set the full-scale range of each output. Each DAC
output has 127 sink and 127 source steps that are pro-
grammed by the I2C interface. Power-supply tracking
functionality is provided for three channels using dedi-
cated control inputs. Once power-supply tracking is
accomplished, the current outputs default to zero. Two
address pins allow up to four DS4426 devices to exist
on the same I2C bus.
Applications
Power-Supply Adjustment
Power-Supply Margining
Power-Supply Tracking
Adjustable Current Sink or Source
Features
♦ Four Current DACs
50µA to 200µA Adjustable Full-Scale Range
127 Settings Each for Sink and Source
♦ Power-Supply Tracking
Power-Supply Sequencing
Ramp-Up and Ramp-Down Tracking Control
Ratiometric Tracking Support
♦ +2.7V to +5.5V Operation
♦ I2C-Compatible Serial Interface
♦ Two Address Input Pins Allow Up to Four Devices
on Same I2C Bus
♦ Lead-Free, 28-Pin TQFN Package (4mm x 4mm)
with Exposed Pad
♦ Industrial Temperature Range: -40°C to +85°C
TOP VIEW
Pin Configuration
21 20 19 18 17 16 15
FS1 22
FS2 23
FS3 24
GAIN3 25
GAIN2 26
DS4426
GAIN1 27
N.C. 28
+
*EP
14 INN2
13 INP2
12 INN1
11 INP1
10 A1
9 A0
8 GND
1 234567
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS4426T+
-40°C to +85°C
28 TQFN-EP*
DS4426T+T&R
-40°C to +85°C
28 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
Functional Diagram appears at end of data sheet.
*EXPOSED PAD.
THIN QFN
(4mm × 4mm)
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
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Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
(TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
600
SDA = SCL = THR[3:1] = VCC
575 GAIN[3:1] = FS[3:0] = OUT[3:0] = OPEN
INP[3:1] = INN[3:1] = GND
550
525
500
475
450
425
400
2.5
3.0 3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)
5.5
VOLTCO (SINK)
250
40kΩ LOAD ON FS[3:0].
VCC = +5.5V
225
200
175
SDA = SCL = THR[3:1] = VCC
GAIN[3:1] = OPEN
INP[3:1] = INN[3:1] = GND
150
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VOUT (V)
SUPPLY CURRENT
vs. TEMPERATURE
600
575 VCC = +5.5V
550 VCC = +3.3V
525
500
475
VCC = +2.7V
450
SDA = SCL = THR[3:1] = VCC
425 GAIN[3:1] = FS[3:0] = OUT[3:0] = OPEN
INP[3:1] = INN[3:1] = GND
400
-40 -20 0 20 40 60
TEMPERATURE (°C)
80
TEMPERATURE COEFFICIENT
vs. SETTING (SOURCE)
300
RANGE FOR THE 50μA TO 200μA
250 CURRENT SOURCE RANGE
200
150
+25°C TO -40°C
100
50
0
-50
0
+25°C TO +85°C
25 50 75 100 125
SETTING (DEC)
VOLTCO (SOURCE)
-150
40kΩ LOAD ON FS[3:0].
VCC = +5.5V
-175
-200
-225
SDA = SCL = THR[3:1] = VCC
GAIN[3:1] = OPEN
INP[3:1] = INN[3:1] = GND
-250
012345
VOUT (V)
TEMPERATURE COEFFICIENT
vs. SETTING (SINK)
650
RANGE FOR THE 50μA TO 200μA
550 CURRENT SINK RANGE
450
350
250
150 +25°C TO -40°C
50
+25°C TO +85°C
-50
-150
-250
0
25 50 75 100 125
SETTING (DEC)
INTEGRAL LINEARITY
1.0
RANGE FOR THE 50μA TO 200μA
0.8 CURRENT SOURCE AND SINK RANGE
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
25 50 75 100
SETTING (DEC)
125
DIFFERENTIAL LINEARITY
1.0
RANGE FOR THE 50μA TO 200μA
0.8 CURRENT SOURCE AND SINK RANGE
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
25 50 75 100
SETTING (DEC)
125
_______________________________________________________________________________________ 5
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Quad-Channel, I2C-Margining IDACs with
Three Channels of Power-Supply Tracking
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to
describe I2C data transfers:
I2C Slave Address: The slave address of the
DS4426 is determined by the state of the A0 and A1
pins (see Table 1).
Master Device: The master device controls the slave
devices on the bus. The master device generates
SCL clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive
data at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states. When the bus is
idle it often initiates a low-power mode for slave
devices.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 3 for applicable timing.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL
remains high generates a STOP condition. See
Figure 3 for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one.
Repeated STARTs are commonly used during read
operations to identify a specific memory address to
begin a data transfer. A repeated START condition
is issued identically to a normal START condition.
See Figure 6 for applicable timing.
Bit Write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL,
plus the setup-and-hold time requirements (Figure
6). Data is shifted into the device during the rising
edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time (Figure 6) before the next rising edge
of SCL during a bit read. The device shifts out each
bit of data on SDA at the falling edge of the previous
SCL pulse, and the data bit is valid at the rising
edge of the current SCL pulse. Remember that the
master generates all SCL clock pulses, including
when it is reading bits from the slave.
Acknowledgement (ACK and NACK): An
Acknowledgement (ACK) or Not Acknowledge
(NACK) is always the ninth bit transmitted during a
byte transfer. The device receiving data (the master
during a read or the slave during a write operation)
performs an ACK by transmitting a zero during the
ninth bit. A device performs a NACK by transmitting
a 1 during the ninth bit. Timing for the ACK and
NACK is identical to all other bit writes (Figure 6). An
ACK is the acknowledgment that the device is prop-
erly receiving data. A NACK is used to terminate a
read sequence or as an indication that the device is
not receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgement
from the slave to the master. The 8 bits transmitted
by the master are done according to the bit-write def-
inition, and the acknowledgement is read using the
bit-read definition.
Byte Read: A byte read is an 8-bit information trans-
fer from the slave to the master plus a 1-bit ACK or
NACK from the master to the slave. The 8 bits of
information that are transferred (most significant bit
first) from the slave to the master are read by the
master using the bit-read definition, and the master
transmits an ACK using the bit-write definition to
receive additional data bytes. The master must
NACK the last byte read to terminate communication
so the slave returns control of SDA to the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit. The
DS4426’s slave address is determined by the state
of the A0 and A1 pins (see Table 1). When the R/W
bit is 0 (such as in 90h), the master is indicating it
will write data to the slave. If R/W = 1 (91h in this
case), the master is indicating it wants to read from
the slave. If an incorrect slave address is written, the
DS4426 assumes the master is communicating with
another I2C device and ignores the communication
until the next START condition is sent.
Memory Address: During an I2C write operation,
the master must transmit a memory address to iden-
tify the memory location where the slave is to store
the data. The memory address is always the second
byte transmitted during a write operation following
the slave address byte.
______________________________________________________________________________________ 11
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet DS4426.PDF ] | |
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