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P89LPC9301A1 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer P89LPC9301A1
Beschreibung 8-bit Microcontroller
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
P89LPC9301A1 Datasheet, Funktion
www.DataSheet4U.com
P89LPC9301/931A1
8-bit microcontroller with accelerated two-clock 80C51 core
4 kB/8 kB 3 V byte-erasable flash
Rev. 01 — 9 April 2009
Preliminary data sheet
1. General description
The P89LPC9301/931A1 is a single-chip microcontroller, available in low cost packages,
based on a high performance processor architecture that executes instructions in two to
four clocks, six times the rate of standard 80C51 devices. Many system-level functions
have been incorporated into the P89LPC9301/931A1 in order to reduce component count,
board space, and system cost.
2. Features
2.1 Principal features
I 4 kB/8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte
pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
I 256-byte RAM data memory.
I Two analog comparators with selectable inputs and reference source.
I Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output).
I A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit
prescaler and a programmable and readable 16-bit timer.
I Enhanced UART with a fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port and SPI communication port.
I 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
I Enhanced low voltage (brownout) detect allows a graceful system shutdown when
power fails.
I 28-pin TSSOP and PLCC packages with 23 I/O pins minimum and up to 26 I/O pins
while using on-chip oscillator and reset options.
2.2 Additional features
I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequency for the same performance results in power savings and reduced
EMI.
I Serial flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs.






P89LPC9301A1 Datasheet, Funktion
www.DNatXaSPheSete4Um.coicmonductors
6. Pinning information
6.1 Pinning
P89LPC9301/931A1
8-bit microcontroller with accelerated two-clock 80C51 core
P2.0 1
P2.1 2
P0.0/CMP2/KBI0 3
P1.7 4
P1.6 5
P1.5/RST 6
VSS 7
P3.1/XTAL1 8
P3.0/XTAL2/CLKOUT 9
P1.4/INT1 10
P1.3/INT0/SDA 11
P1.2/T0/SCL 12
P2.2/MOSI 13
P2.3/MISO 14
P89LPC9301FDH
P89LPC931A1FDH
28 P2.7
27 P2.6
26 P0.1/CIN2B/KBI1
25 P0.2/CIN2A/KBI2
24 P0.3/CIN1B/KBI3
23 P0.4/CIN1A/KBI4
22 P0.5/CMPREF/KBI5
21 VDD
20 P0.6/CMP1/KBI6
19 P0.7/T1/KBI7
18 P1.0/TXD
17 P1.1/RXD
16 P2.5/SPICLK
15 P2.4/SS
002aae451
Fig 3. P89LPC9301/931A1 TSSOP28 pin configuration
P89LPC9301_931A1_1
Preliminary data sheet
Rev. 01 — 9 April 2009
© NXP B.V. 2009. All rights reserved.
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Table 4. Special function registers …continued
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
addr. MSB
LSB
Reset value
Hex Binary
FMCON Program flash E4H BUSY
-
-
-
HVA
HVE
SV
OI 70
0111 0000
control (Read)
Program flash E4H FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 FMCMD.3 FMCMD.2 FMCMD.1 FMCMD.0
control (Write)
FMDATA
Program flash E5H
data
00 0000 0000
I2ADR
I2C-bus slave
address
register
DBH I2ADR.6
I2ADR.5
I2ADR.4
I2ADR.3
I2ADR.2
I2ADR.1
I2ADR.0
GC 00
0000 0000
Bit address DF DE DD DC DB DA D9 D8
I2CON*
I2C-bus control D8H
register
-
I2EN STA STO
SI
AA
-
CRSEL 00
x000 00x0
I2DAT
I2C-bus data
register
DAH
I2SCLH
Serial clock
generator/SCL
duty cycle
register high
DDH
00 0000 0000
I2SCLL
Serial clock
generator/SCL
duty cycle
register low
DCH
00 0000 0000
I2STAT
I2C-bus status D9H STA.4
STA.3
STA.2
STA.1
STA.0
0
0
0 F8 1111 1000
register
Bit address AF AE AD AC AB AA A9 A8
IEN0*
Interrupt
enable 0
A8H EA
EWDRT
EBO
ES/ESR
ET1
EX1
ET0
EX0 00
0000 0000
Bit address EF EE ED EC EB EA E9 E8
IEN1*
Interrupt
E8H -
EST
-
enable 1
-
ESPI
EC
EKBI
EI2C 00[1] 00x0 0000
Bit address BF BE BD BC BB BA B9 B8
IP0*
Interrupt
B8H -
PWDRT
PBO
PS/PSR
PT1
PX1
PT0
PX0 00[1] x000 0000
priority 0

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