PDF P89LPC9301 Data sheet ( Hoja de datos )

Número de pieza	P89LPC9301
Descripción	8-bit Microcontroller
Fabricantes	NXP Semiconductors
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No Preview Available ! www.DataSheet4U.com P89LPC9301/931A1 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable ﬂash Rev. 01 — 9 April 2009 Preliminary data sheet 1. General description The P89LPC9301/931A1 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC9301/931A1 in order to reduce component count, board space, and system cost. 2. Features 2.1 Principal features I 4 kB/8 kB byte-erasable ﬂash code memory organized into 1 kB sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. I 256-byte RAM data memory. I Two analog comparators with selectable inputs and reference source. I Two 16-bit counter/timers (each may be conﬁgured to toggle a port output upon timer overﬂow or to become a PWM output). I A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit prescaler and a programmable and readable 16-bit timer. I Enhanced UART with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I2C-bus communication port and SPI communication port. I 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V). I Enhanced low voltage (brownout) detect allows a graceful system shutdown when power fails. I 28-pin TSSOP and PLCC packages with 23 I/O pins minimum and up to 26 I/O pins while using on-chip oscillator and reset options. 2.2 Additional features I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. I Serial ﬂash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. 1 page www.DNatXaSPheSete4Um.coicmonductors 5. Functional diagram P89LPC9301/931A1 8-bit microcontroller with accelerated two-clock 80C51 core VDD VSS KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7 CLKOUT CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 T1 XTAL2 XTAL1 PORT 0 PORT 3 Fig 2. Functional diagram P89LPC9301/ 931A1 PORT 1 TXD RXD T0 INT0 INT1 RST SCL SDA PORT 2 MOSI MISO SS SPICLK 002aae448 P89LPC9301_931A1_1 Preliminary data sheet Rev. 01 — 9 April 2009 © NXP B.V. 2009. All rights reserved. 5 of 65 5 Page xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 4. Special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB LSB Reset value Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 E0 ACC* Accumulator E0H 00 0000 0000 AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0 - DPS 00 0000 00x0 Bit address F7 F6 F5 F4 F3 F2 F1 F0 B* B register F0H 00 0000 0000 BRGR0[2] Baud rate generator 0 rate low BEH 00 0000 0000 BRGR1[2] Baud rate generator 0 rate high BFH 00 0000 0000 BRGCON Baud rate BDH - - - - - - SBRGS BRGEN 00[2] xxxx xx00 generator 0 control CMP1 Comparator 1 ACH control register - - CE1 CP1 CN1 OE1 CO1 CMF1 00[1] xx00 0000 CMP2 Comparator 2 ADH control register - - CE2 CP2 CN2 OE2 CO2 CMF2 00[1] xx00 0000 DIVM CPU clock divide-by-M control 95H 00 0000 0000 DPTR Data pointer (2 bytes) DPH Data pointer high 83H 00 0000 0000 DPL Data pointer 82H low 00 0000 0000 FMADRH Program ﬂash E7H address high 00 0000 0000 FMADRL Program ﬂash E6H address low 00 0000 0000 11 Page

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