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PDF P89LPC9402 Data sheet ( Hoja de datos )
| Número de pieza | P89LPC9402 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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P89LPC9402
8-bit microcontroller with accelerated two-clock 80C51 core
8 kB 3 V byte-erasable flash with 32 segment 4 LCD driver
Rev. 00.01 — 8 April 2009
Preliminary data sheet
1. General description
The P89LPC9402 is a multi-chip module consisting of a P89LPC931A1 single-chip
microcontroller combined with a PCF8576D universal LCD driver in a low-cost 64-pin
package. The LCD driver provides 32 segments and supports from 1 to 4 backplanes.
Display overhead is minimized by an on-chip display RAM with auto-increment
addressing.
2. Features
2.1 Principal features
8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages.
Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
256-byte RAM data memory.
32 segment × 4 backplane LCD controller supports from 1 to 4 backplanes.
Two analog comparators with selectable inputs and reference source.
Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output).
A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit
prescaler and a programmable and readable 16-bit timer.
Enhanced UART with a fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port and SPI communication port.
2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
Enhanced low voltage (brownout) detect allows a graceful system shutdown when
power fails.
64-pin LQFP package with 20 microcontroller I/O pins minimum and up to 23
microcontroller I/O pins while using on-chip oscillator and reset options.
2.2 Additional features
A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequency for the same performance results in power savings and reduced
EMI.
1 page  
NXP Semiconductors
www.DataSheet4U.com
P89LPC9402
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC931A1
ACCELERATED 2-CLOCK 80C51 CPU
P3[1:0]
P2.5, P2[3:0]
P1[7:0]
P0[7:0]
8 kB CODE FLASH
256-BYTE
DATA RAM
internal bus
PORT 3
CONFIGURABLE I/Os
PORT 2
CONFIGURABLE I/Os
PORT 1
CONFIGURABLE I/Os
PORT 0
CONFIGURABLE I/Os
KEYPAD
INTERRUPT
WATCHDOG TIMER
AND OSCILLATOR
UART
I2C-BUS
SPI
REAL-TIME CLOCK/
SYSTEM TIMER
TIMER 0
TIMER 1
ANALOG
COMPARATORS
TXD
RXD
SCL
SDA
SPICLK
MOSI
MISO
T0
T1
CMP2
CIN2B
CIN2A
CMP1
CIN1A
CIN1B
XTAL1
CRYSTAL
OR
RESONATOR
XTAL2
PROGRAMMABLE
OSCILLATOR DIVIDER
CONFIGURABLE
OSCILLATOR
Fig 2. Microcontroller section block diagram
CPU
clock
ON-CHIP RC
OSCILLATOR
WITH CLOCK DOUBLER
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
002aae471
P89LPC9402_0.01
Preliminary data sheet
Rev. 00.01 — 8 April 2009
© NXP B.V. 2009. All rights reserved.
5 of 60
5 Page 
NXP Semiconductors
www.DataSheet4U.com
P89LPC9402
8-bit microcontroller with accelerated two-clock 80C51 core
7. Functional description
Remark: Please refer to the P89LPC9402 User manual for a more detailed functional
description.
7.1 Special function registers
Remark: Special Function Registers (SFRs) accesses are restricted in the following
ways:
• User must not attempt to access any SFR locations not defined.
• Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
• SFR bits labeled ‘-’, logic 0 or logic 1 can only be written and read as follows:
– ‘-’ Unless otherwise specified, must be written with logic 0, but can return any
value when read (even if it was written with logic 0). It is a reserved bit and may be
used in future derivatives.
– Logic 0 must be written with logic 0, and will return a logic 0 when read.
– Logic 1 must be written with logic 1, and will return a logic 1 when read.
P89LPC9402_0.01
Preliminary data sheet
Rev. 00.01 — 8 April 2009
© NXP B.V. 2009. All rights reserved.
11 of 60
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