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PDF ADCLK846 Data sheet ( Hoja de datos )
| Número de pieza | ADCLK846 | |
| Descripción | 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Selectable LVDS/CMOS outputs
Up to 6 LVDS (1.2 GHz) or 12 CMOS (250 MHz) outputs
<16 mW per channel (100 MHz operation)
54 fs integrated jitter (12 kHz to 20 MHz)
100 fs additive broadband jitter
2.0 ns propagation delay (LVDS)
135 ps output rise/fall (LVDS)
65 ps output-to-output skew (LVDS)
Sleep mode
Pin-programmable control
1.8 V power supply
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
GENERAL DESCRIPTION
The ADCLK846 is a 1.2 GHz/250 MHz, LVDS/CMOS, fanout
buffer optimized for low jitter and low power operation. Possible
configurations range from 6 LVDS to 12 CMOS outputs,
including combinations of LVDS and CMOS outputs. Two
control lines are used to determine whether fixed blocks of
outputs are LVDS or CMOS outputs.
1.8 V, 6 LVDS/12 CMOS Outputs
Low Power Clock Fanout Buffer
ADCLK846
FUNCTIONAL BLOCK DIAGRAM
ADCLK846
LVDS/CMOS
VREF
CLK
CLK
CTRL_A
LVDS/CMOS
CTRL_B
SLEEP
OUT0 (OUT0A)
OUT0 (OUT0B)
OUT1 (OUT1A)
OUT1 (OUT1B)
OUT2 (OUT2A)
OUT2 (OUT2B)
OUT3 (OUT3A)
OUT3 (OUT3B)
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
Figure 1.
The clock input accepts various types of single-ended and
differential logic levels including LVPECL, LVDS, HSTL, CML,
and CMOS.
Table 8 provides interface options for each type of connection.
The SLEEP pin enables a sleep mode to power down the device.
This device is available in a 24-pin LFCSP package. It is specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
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CLOCK CHARACTERISTICS
Table 3. Clock Output Phase Noise
Parameter
CLK-TO-LVDS ABSOLUTE PHASE NOISE
1000 MHz
CLK-TO-CMOS ABSOLUTE PHASE NOISE
200 MHz
ADCLK846
Min Typ Max Unit
−90
−108
−117
−126
−134
−141
−146
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−100
−117
−128
−138
−147
−153
−156
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Conditions
Input slew rate > 1 V/ns
At 10 Hz offset
At 100 Hz offset
At 1 kHz offset
At 10 kHz offset
At 100 kHz offset
At 1 MHz offset
At 10 MHz offset
Input slew rate > 1 V/ns
At 10 Hz offset
At 100 Hz offset
At 1 kHz offset
At 10 kHz offset
At 100 kHz offset
At 1 MHz offset
At 10 MHz offset
LOGIC AND POWER CHARACTERISTICS
Table 4. Control Pin Characteristics
Parameter
Symbol Min
Typ Max Unit Conditions
CONTROL PINS
(CTRL_A, CTRL_B, SLEEP)1
Logic 1 Voltage
VIH VS − 0.4
V
Logic 0 Voltage
VIL
0.4 V
Logic 1 Current
IIH 5 8 20 μA
Logic 0 Current
IIL −5
+5 μA
Capacitance
2 pF
POWER
Supply Voltage Requirement
VS
1.71 1.8 1.89 V
VS = 1.8 V ± 5%
LVDS Outputs, Full Operation
LVDS at 100 MHz
55 70 mA All outputs enabled as LVDS and loaded, RL = 100 Ω
LVDS at 1200 MHz
110 130 mA All outputs enabled as LVDS and loaded, RL = 100 Ω
CMOS Outputs, Full Operation
CMOS at 100 MHz
75 95 mA
All outputs enabled as CMOS and loaded,
CMOS load = 10 pF
CMOS at 250 MHz
155 190 mA
All outputs enabled as CMOS and loaded,
CMOS load = 10 pF
Sleep
3 mA SLEEP pin pulled high; does not include power
dissipated in external resistors
Power Supply Rejection2
LVDS
PSRTPD
0.9 ps/mV
CMOS
PSRTPD
1.2 ps/mV
1 These pins each have a 200 kΩ internal pull-down resistor.
2 Change in TPD per change in VS.
Rev. A | Page 5 of 16
5 Page 
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ADCLK846
FUNCTIONAL DESCRIPTION
The ADCLK846 clock input is distributed to all output channels.
Each channel bank is pin programmable for either LVDS or
CMOS levels. This allows the selection of multiple logic
configurations ranging from 6 LVDS to 12 CMOS outputs,
along with other combinations using both types of logic.
CLOCK INPUTS
The differential inputs of the ADCLK846 are internally self-
biased. The clock inputs have a resistor divider, which sets the
common-mode level for the inputs. The complementary inputs
are biased about 30 mV lower than the true input to avoid
oscillations if the input signal ceases. See Figure 20 for
the equivalent input circuit.
The inputs can be ac-coupled or dc-coupled. Table 8 displays
a guide for input logic compatibility. If a single-ended input is
desired, this can be accommodated by ac or dc coupling to one
side of the differential input. Bypass the other input to ground
by a capacitor.
Note that jitter performance degrades with low input slew rate,
as shown in Figure 11. See Figure 28 through Figure 32 for
different termination schemes.
VS
9kΩ 9.5kΩ
CLK
9kΩ
CLK
8.5kΩ
GND
Figure 20. ADCLK846 Input Stage
AC-COUPLED APPLICATIONS
When ac coupling is desired, the ADCLK846 offers two
options. The first option requires no external components
(excluding the dc blocking capacitor); it allows the user to
couple the reference signal onto the clock input pins (see
Figure 31).
The second option allows the use of the VREF pin to set the dc
bias level for the ADCLK846. The VREF pin can be connected
to CLK and CLK through resistors. This method allows lower
impedance termination of signals at the ADCLK846 (see
Figure 32).
The internal bias resistors are still in parallel with the external
biasing. However, the relatively high impedance of the internal
resistors allows the external termination to VREF to dominate.
This is also useful if it is not desirable to offset the inputs slightly
as previously mentioned using only the internal biasing.
Table 8. Input Logic Compatibility
Supply (V)
Logic
Common Mode (V)
3.3 CML 2.9
2.5 CML 2.1
1.8 CML 1.4
3.3
CMOS
1.65
2.5
CMOS
1.25
1.8
CMOS
0.9
1.5
HSTL
0.75
LVDS
1.25
3.3
LVPECL
2.0
2.5
LVPECL
1.2
1.8
LVPECL
0.5
Output Swing (V)
0.8
0.8
0.8
3.3
2.5
1.8
0.75
0.4
0.8
0.8
0.8
AC-Coupled
Yes
Yes
Yes
Not allowed
Not allowed
Yes
Yes
Yes
Yes
Yes
Yes
DC-Coupled
Not allowed
Not allowed
Yes
Not allowed
Not allowed
Yes
Yes
Yes
Not allowed
Yes
Yes
Rev. A | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADCLK846.PDF ] | |
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