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PDF ADP5020 Data sheet ( Hoja de datos )
| Número de pieza | ADP5020 | |
| Descripción | Power Management Unit | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Input voltage range: 2.4 V to 5.5 V
Low standby current: 1 μA
Switching frequency: 3 MHz
I2C interface
Synchronous Buck 1 regulator: 600 mA
Synchronous Buck 2 regulator: 250 mA
Low dropout regulator (LDO): 150 mA
Internal compensation
Internal soft start
Thermal shutdown
20-lead 4 mm × 4 mm LFCSP
APPLICATIONS
Digital cameras, handsets
Mobile TVs
GENERAL DESCRIPTION
The ADP5020 provides a highly integrated power solution that
includes all of the power circuits necessary for a digital imaging
module. It comprises two step-down dc-to-dc converters, one
LDO, and a power sequence controller. All dc-to-dc converters
integrate power pMOSFETs and nMOSFETs, making the system
simpler and more compact and reducing the cost. The ADP5020
has digitally programmed output voltages and buck converters
that can source up to 600 mA. A fixed frequency operation of
3 MHz enables the use of tiny inductors and capacitors. The buck
converters use a voltage mode, constant-frequency PWM control
scheme, and the synchronous rectification is implemented to
reduce the power loss. The Buck 1 regulator operates at up to
93% efficiency.
Power Management Unit
for Imaging Modules
ADP5020
TYPICAL APPLICATIONS CIRCUIT
VIN
2.4V TO 5.5V
10µF
VDD_IO
1µF
1.7V TO 3.6V
10kΩ 10kΩ
0.1µF
VDD1
SW1
VDD2
VOUT1
VOUT1
VDD3
PGND1
ADP5020
VDDA
SW2
VOUT2
VDD_IO
PGND2
SDA
VOUT3
2.2µH
VOUT1
2.5V TO 3.7V
10µF
VOUT2
2.2µH 1.1V TO 1.8V
4.7µF
VOUT3
1.8V TO 3.3V
1µF
SCL
XSHTDN
EN/GPIO
SYNC
EXT. FREQ
9.6/19.2MHz
DGND AGND
Figure 1.
The ADP5020 provides high performance, reduces component
count and size, and is lower in cost when compared to conven-
tional designs.
The ADP5020 runs on input voltage from 2.4 V to 5.5 V and
supports one-cell lithium-ion (Li+) batteries. The high perfor-
mance LDO maximizes noise suppression. The ADP5020 can be
activated via an I2C® interface or through a dedicated enable input.
During logic-controlled shutdown, the input is disconnected
from the output source, and the part draws 1 μA typical from
the input source. Other key features include undervoltage lockout
to prevent deep-battery discharge and soft start to prevent input
current overshoot at startup. The ADP5020 is available in a
20-lead LFCSP.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
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SWITCHING SPECIFICATIONS
Table 2.
Parameter
SWITCHING FREQUENCY
CH1
CH2
SYNC CLOCK DIVIDER RATIO
SYNC CHARACTERISTICS
Frequency Range
Frequency Duty Cycle
Signal
DC Coupling Level
Low Level Input Voltage
High Level Input Voltage
DC Coupling
AC Coupling Level
AC Coupling Capacitor
Input Current
Symbol Conditions
fSW1 Sync disabled
fSW2 Sync disabled
RATIODIV SYNC_9P6 = 1
RATIODIV SYNC_19P2 = 1
fSYNC1
fSYNC2
fSYNCDUTY
VIL
VIH
VSYNC
VCAC-PP
ISYNC
Sine wave, peak-to-peak
SYNC_9P6 = 1, or SYNC_19P2 = 1
ADP5020
Min
Typ Max
Unit
2.5
3 3.6
MHz
2.5
3 3.6
MHz
3
6
9.6 MHz
19.2 MHz
40
50 60
%
0.7 × VDD_IO
0
0.5
1.0
10
50
0.3 × VDD_IO
VDD_IO
VDD_IO
V
V
V
V
nF
μA
DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 1 REGULATOR
Table 3.
Parameter
OUTPUT VOLTAGE
Range1
Initial Accuracy
Total Accuracy
VOUT1 REGULATION
Load Regulation
Line Regulation
CURRENT
Maximum Output Current
Quiescent Current
POWER
Low-Side Power nMOSFET
High-Side Power pMOSFET
SWITCH CURRENT LIMIT
MINIMUM ON TIME
MAXIMUM DUTY CYCLE
SOFT START TIME
COUT DISCHARGE SWITCH ON RESISTANCE
Symbol Conditions
VOUT1
3-bit range
TA = 25°C, VDD12, VOUT1 = 3.3 V, ILOAD = 20 mA
VDD13, ILOAD = 50 mA to 600 mA
ILOAD = 20 mA to 600 mA
VDDA = 1.8 V, VDD12, 3
IBK1MAX
IQBK1
VDD13, VOUT1 = 2.5 V to 3.7 V
ILOAD = 0 mA
RDSON1
RDSON1
ICL1
tMIN1
DMAX1
tSS1
RDIS1
ID = 400 mA
ID = 400 mA
Min
2.5
−1
−5
0.8
0.7
Typ
0.2
0.15
4
175
250
1.2
55
88
1.4
1
1 See Table 13 (the BUCK1_VSEL register, Address 0x01) for details.
2 VDD1 = 3.1 V to 5.5 V, ILOAD is less than 200 mA. For tight regulation, the supply voltage must be 0.6 V higher than the output voltage.
3 VDD1 = 3.7 V to 5.5 V, ILOAD is more than 200 mA. For tight regulation, the supply voltage must be 1.2 V higher than the output voltage.
Max
3.7
+1
+4
600
6
250
400
1.6
95
1.3
Unit
V
%
%
%
%
mA
mA
mΩ
mΩ
A
ns
%
ms
kΩ
Rev. 0 | Page 5 of 28
5 Page 
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ADP5020
VIN = 4.5 V, VOUT1 = 2.8 V, VOUT2 = VOUT3 = 1.8 V, IOUT = 100 mA, C4 = C1 = 10 μF, C2 = 4.7 μF, C3 = 1 μF, TJ = 25°C, unless otherwise noted.
0.90
BUCK 1 OUTPUT = 2V/DIV
0.85 BUCK 2 OUTPUT = 1V/DIV
0.80
0.75 TIME = 5ms/DIV
0.70
0.65
0.60
0.55
0.50
0
EFF1 (1.1V)
EFF2 (1.2V)
EFF3 (1.3V)
EFF4 (1.4V)
EFF5 (1.5V)
EFF6 (1.6V)
EFF7 (1.7V)
EFF8 (1.8V)
50 100 150 200 250 300
LOAD CURRENT (mA)
BUCK 2
ENABLE
Figure 12. Buck 2 Efficiency vs. Load Current
Figure 15. Startup Sequence of the Three Regulators, Set by Default
BUCK 2 OUTPUT = 50mV/DIV
ILOAD = 100mA/DIV
TIME = 100µs/DIV
BUCK 2 OUTPUT = 1V/DIV
SW2 OUTPUT = 2V/DIV
TIME = 500µs/DIV
BUCK 2
BUCK 2
ILOAD
Figure 13. Buck 2 Load Transient Response
1.2
1.0
0.8
0.6
ISHTDN (µA) @ –40°C
ISHTDN (µA) @ +25°C
0.4 ISHTDN (µA) @ +125°C
0.2
0
2.0 2.5 3.0 3.5 4.0 4.5
INPUT VOLTAGE (V)
Figure 14. Shutdown Current vs. Input Voltage
5.0
SW2
Figure 16. Buck 2 Enable Startup
BUCK 1 OUTPUT = 1V/DIV
SW1 OUTPUT = 2V/DIV
TIME = 500µs/DIV
BUCK 1
SW1
Figure 17. Buck 1 Enable Startup
Rev. 0 | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ADP5020.PDF ] | |
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