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PDF ADP3182 Data sheet ( Hoja de datos )
| Número de pieza | ADP3182 | |
| Descripción | Adjustable Output 1-/2-/3-Phase Synchronous Buck Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Selectable 1-, 2-, or 3-phase operation at up to 1 MHz per
phase
±2% worst-case differential sensing error over temperature
Externally adjustable 0.8 V to >5 V output from a 12 V supply
Logic-level PWM outputs for interface to external high
power drivers
Active current balancing between all output phases
Built-in power good/crowbar functions
Programmable short-circuit protection with programmable
latch-off delay
APPLICATIONS
Auxiliary supplies
DDR memory supplies
Point-of-load modules
Adjustable Output 1-/2-/3-Phase
Synchronous Buck Controller
ADP3182
GENERAL DESCRIPTION
The ADP3182 is a highly efficient multiphase, synchronous,
buck-switching regulator controller optimized for converting a
12 V main supply into a high current, low voltage supply for use
in point-of-load (POL) applications. It uses a multimode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VR size and
efficiency. The phase relationship of the output signals can be
programmed to provide 1-, 2-, or 3-phase operation, allowing
for the construction of up to three complementary buck-
switching stages. The ADP3182 also provides accurate and
reliable short-circuit protection and adjustable current limiting.
ADP3182 is specified over the commercial temperature range of
0°C to +85°C and is available in a 20-lead QSOP package.
FUNCTIONAL BLOCK DIAGRAM
VCC
1
RAMPADJ RT
98
EN 6
UVLO
SHUTDOWN
& BIAS
GND 14
950mV
OSCILLATOR
CMP
SET EN
RESET
20 PWM1
FB
650mV
CURRENT
BALANCING
CIRCUIT
CMP
CMP
RESET
2 / 3-PHASE
DRIVER LOGIC
RESET
19 PWM2
18 PWM3
PWRGD 5
DELAY
ILIMIT 10
EN
DELAY 7
SOFT
START
1.05V
FB
CROWBAR
CURRENT
LIMIT
CIRCUIT
CURRENT
LIMIT
17 SW1
16 SW2
15 SW3
12 CSSUM
11 CSREF
13 CSCOMP
COMP 4
3 FB
ADP3182
800mV
REFERENCE
2
FBRTN
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
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TEST CIRCUITS
12V
39kΩ
1kΩ
0.8V
ADP3182
1 VCC
CSCOMP
13
100nF
CSSUM
12
CSREF
11
14 GND
VOS = CSCOMP –0.8V
40
Figure 2. Current Sense Amplifier VOS
ADP3182
Rev. 0 | Page 5 of 20
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After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops
below 1.8 V. The current limit latch-off delay time is therefore
set by the RC time constant discharging from 3 V to 1.8 V.
Typical overcurrent latch-off waveforms are shown in Figure 7.
Because the controller continues to cycle the phases during the
latch-off delay time, the controller returns to normal operation
if the short is removed before the 1.8 V threshold is reached.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if a short circuit has
caused the output voltage to drop below the PWRGD threshold,
a soft start cycle is initiated.
The latch-off function can be reset by either removing and
reapplying VCC to the ADP3182, or by pulling the EN pin low
for a short time. To disable the short-circuit latch-off function,
the external resistor to ground should be left open, and a high-
value (>1 MΩ) resistor should be connected from DELAY to
VCC. This prevents the DELAY capacitor from discharging, so
the 1.8 V threshold is never reached. The resistor has an impact
on the soft start time because the current through it adds to the
internal 20 µA current source.
During start-up when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage to
the PWM comparators to 2 V. This limits the voltage drop
across the low-side MOSFETs through the current balance
circuitry.
An inherent per phase current limit protects individual phases
if one or more phases stop functioning because of a faulty
component. This limit is based on the maximum normal mode
COMP voltage.
POWER GOOD MONITORING
The power good comparator monitors the output voltage via the
FB pin. The PWRGD pin is an open-drain output whose high
level (when connected to a pull-up resistor) indicates that the
output voltage is within the nominal limits specified in the
electrical table. PWRGD goes low if the output voltage is
outside this specified range or the EN pin is pulled low. Figure 8
shows the PWRGD output response when the input power is
removed from the regulator.
ADP3182
Figure 7. Overcurrent Latch-Off Waveforms
Channel 1: CSREF, Channel 2: COMP,
Channel 3: Phase 1 Switch Node, Channel 4: DELAY
Figure 8. Shutdown Waveforms
Channel 1: CSREF, Channel 2: DELAY,
Channel 3: PWRGD, Channel 4: COMP
OUTPUT CROWBAR
As part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) when the output voltage exceeds the upper
crowbar threshold. This crowbar action stops once the output
voltage falls below the release threshold of approximately 650 mV.
Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output over-
voltage is due to a short in the high-side MOSFET, this action
limits the current of the input supply or blows the fuse to
protect the microprocessor from being destroyed.
Rev. 0 | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADP3182.PDF ] | |
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