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WSE128K16-xxx Schematic ( PDF Datasheet ) - White Electronic Designs Corporation

Teilenummer WSE128K16-xxx
Beschreibung 128Kx16 SRAM/EEPROM MODULE
Hersteller White Electronic Designs Corporation
Logo White Electronic Designs Corporation Logo 




Gesamt 15 Seiten
WSE128K16-xxx Datasheet, Funktion
White Electronic Designs
www.DataSheet4U.com
WSE128K16-XXX
PRELIMINARY*
128Kx16 SRAM/EEPROM MODULE
FEATURES
Access Times of 35ns (SRAM) and 150ns (EEPROM)
Access Times of 45ns (SRAM) and 120ns (EEPROM)
Access Times of 70ns (SRAM) and 300ns (EEPROM)
Packaging
• 66 pin, PGA Type, 1.075" square HIP, Hermetic
Ceramic HIP (H1) (Package 400)
Commercial, Industrial and Military Temperature
Ranges
TTL Compatible Inputs and Outputs
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight - 13 grams typical
EEPROM MEMORY FEATURES
• 68 lead, Hermetic CQFP (G2T), 22mm (0.880")
square (Package 509). Designed to fit JEDEC 68
lead 0.990" CQFJ footprint (FIGURE 2)
128Kx16 SRAM
128Kx16 EEPROM
Organized as 128Kx16 of SRAM and 128Kx16 of
EEPROM Memory with separate Data Buses
Write Endurance 10,000 Cycles
Data Retention at 25°C, 10 Years
Low Power CMOS Operation
Automatic Page Write Operation
Page Write Cycle Time 10ms Max.
Data Polling for End of Write Detection
Both blocks of memory are User Configurable as
256Kx8
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
Low Power CMOS
* This product is under development, is not qualified or characterized and is subject to
change without notice.
FIGURE 1 – WSE128K16-XH1X PIN
CONFIGURATION
Top View
1 12 23
34 45 56
SD8 SWE2# SD15
ED8 VCC ED15
SD9 SCS2# SD14
ED9 ECS2#
ED14
SD10
GND
SD13
ED10 EWE2#
ED13
A13
SD11
SD12
A6 ED11 ED12
A14 A10 OE#
A7 A3 A0
A15 A11 NC
NC A4 A1
PIN DESCRIPTION
ED0-15
SD0-15
A0-16
SWE#1-2
SCS#1-2
OE#
VCC
GND
NC
EWE#1-2
ECS#1-2
EEPROM Data Inputs/Outputs
SRAM Data Inputs/Outputs
Address Inputs
SRAM Write Enable
SRAM Chip Selects
Output Enable
Power Supply
Ground
Not Connected
EEPROM Write Enable
EEPROM Chip Select
A16 A12 SWE#1
NC VCC SD7
SD0 SCS1# SD6
SD1 NC
SD5
A8 A5
A9 EWE1#
ED0 ECS1#
ED1 GND
A2
ED7
ED6
ED5
BLOCK DIAGRAM
OE#
A0-16
SWE1# SCS1#
SWE2# SCS2#
EWE1# ECS1#
EWE2# ECS2#
128K x 8
SRAM
128K x 8
SRAM
128K x 8
EEPROM
128K x 8
EEPROM
SD2 SD3 SD4
11 22
33
ED2 ED3 ED5
44 55 66
8
SD0-7
8
SD8-15
8
ED0-7
8
ED8-15
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






WSE128K16-xxx Datasheet, Funktion
White Electronic Designs
www.DataSheet4U.com
WSE128K16-XXX
PRELIMINARY
EEPROM WRITE
A write cycle is initiated when OE# is high and a low pulse
is on EWE# or ECS# with ECS# or EWE# low. The address
is latched on the falling edge of ECS# or EWE# whichever
occurs last. The data is latched by the rising edge of ECS#
or EWE#, whichever occurs first. A byte write operation
will automatically continue to completion.
WRITE CYCLE TIMING
Figures 7 and 8 show the write cycle timing relationships.
A write cycle begins with address application, write enable
and chip select. Chip select is accomplished by placing the
ECS# line low. Write enable consists of setting the EWE#
line low. The write cycle begins when the last of either
ECS# or EWE# goes low.
The EWE# line transition from high to low also initiates
an internal 150 µsec delay timer to permit page mode
operation. Each subsequent EWE# transition from high
to low that occurs before the completion of the 150 µsec
time out will restart the timer from zero. The operation of
the timer is the same as a retriggerable one-shot.
EEPROM AC WRITE CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Write Cycle Parameter
Symbol Min Max Unit
Write Cycle Time, TYP = 6ms
tWC
10 ms
Address Set-up Time
tAS 0
ns
Write Pulse Width (EWE# or ECS#) tWP 150
ns
Chip Select Set-up Time
tCS 0
ns
Address Hold Time
tAH 100
ns
Data Hold Time
tDH 10
ns
Chip Select Hold Time
tCSH 0
ns
Data Set-up Time
tDS 100
ns
Output Enable Set-up Time
tOES 10
ns
Output Enable Hold Time
tOEH 10
ns
Write Pulse Width High
tWPH 50
ns
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page









WSE128K16-xxx pdf, datenblatt
White Electronic Designs
www.DataSheet4U.com
WSE128K16-XXX
PRELIMINARY
FIGURE 13 – EEPROM SOFTWARE DATA
PROTECTION DISABLE ALGORITHM(1)
EXIT DATA(3)
PROTECT STATE
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
NOTES:
1. Data Format: ED7 - ED0 (Hex);
Address Format: A16 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no other data
is loaded.
3. Write Protect state will be deactivated at end of write period even if no
other data is loaded.
4. 1 to 128 bytes of data may be loaded.
EEPROM SOFTWARE DATA
PROTECTION
A software write protection feature may be enabled
or disabled by the user. When shipped by WEDC, the
WSE128K16-XXX has the feature disabled. Write access
to the device is unrestricted.
To enable software write protection, the user writes three
access code bytes to three special internal locations.
Once write protection has been enabled, each write to the
EEPROM must use the same three byte write sequence
to permit writing. After setting software data protection,
any attempt to write to the device without the three-byte
command sequence will start the internal write timers. No
data will be written to the device, however, for the duration
of twc. The write protection feature can be disabled by
a six byte write sequence of specific data to specific
locations. Power transitions will not reset the software
write protection.
Each 128K byte block of the EEPROM has independent
write protection. One or more blocks may be enabled and
the rest disabled in any combination. The software write
protection guards against inadvertent writes during power
transitions, or unauthorized modification using a PROM
programmer.
EEPROM HARDWARE DATA
PROTECTION
These features protect against inadvertent writes to
the WSE128K16-XXX. These are included to improve
reliability during normal operation:
a) VCC power on delay
As VCC climbs past 3.8V typical the device will wait
5 msec typical before allowing write cycles.
b) VCC sense
While below 3.8V typical write cycles are inhibited.
c) Write inhibiting
Holding OE# low and either ECS# or EWE# high
inhibits write cycles.
d) Noise filter
Pulses of <8ns (typ) on EWE# or ECS# will not
initiate a write cycle.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2005
Rev. 3
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 Page





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