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DS34S101 Schematic ( PDF Datasheet ) - Maxim Integrated Products

Teilenummer DS34S101
Beschreibung (DS34S101 - DS34S108) Single/Dual/Quad/Octal TDM-over-Packet Chip
Hersteller Maxim Integrated Products
Logo Maxim Integrated Products Logo 




Gesamt 13 Seiten
DS34S101 Datasheet, Funktion
Rev: 101708
www.DataSheet4U.com
ABRIDGED DATA SHEET
DS34S101, DS34S102, DS34S104, DS34S108
Single/Dual/Quad/Octal TDM-over-Packet Chip
General Description
These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC
compliant devices allow up to eight E1, T1 or serial
streams or one high-speed E3, T3, STS-1 or serial
stream to be transported transparently over IP, MPLS
or Ethernet networks. Jitter and wander of recovered
clocks conform to G.823/G.824, G.8261, and TDM
specifications. TDM data is transported in up to 64
individually configurable bundles. All standards-
based TDM-over-packet mapping methods are
supported except AAL2. Frame-based serial HDLC
data flows are also supported. The high level of
integration available with the DS34S10x devices
minimizes cost, board space, and time to market.
Applications
TDM Circuit Extension Over PSN
o Leased-Line Services Over PSN
o TDM Over GPON/EPON
o TDM Over Cable
o TDM Over Wireless
Cellular Backhaul Over PSN
Multiservice Over Unified PSN
HDLC-Based Traffic Transport Over PSN
Features
Transport of E1, T1, E3, T3 or STS-1 TDM or
CBR Serial Signals Over Packet Networks
Full Support for These Mapping Methods:
SAToP, CESoPSN, TDMoIP (AAL1), HDLC,
Unstructured, Structured, Structured with CAS
Adaptive Clock Recovery, Common Clock,
External Clock and Loopback Timing Modes
On-Chip TDM Clock Recovery Machines, One
Per Port, Independently Configurable
Clock Recovery Algorithm Handles Network
PDV, Packet Loss, Constant Delay Changes,
Frequency Changes and Other Impairments
64 Independent Bundles/Connections
Multiprotocol Encapsulation Supports IPv4,
IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet
VLAN Support According to 802.1p and 802.1Q
10/100 Ethernet MAC Supports MII/RMII/SSMII
Selectable 32-Bit, 16-Bit or SPI Processor Bus
Operates from Only Two Clock Signals, One for
Clock Recovery and One for Packet Processing
Glueless SDRAM Buffer Management
Low-Power 1.8V Core, 3.3V I/O
See detailed feature list in Section 5 .
TDM
Interfaces
Functional Diagram
CPU
Bus
DS34S108
Circuit
Emulation
Engine
10/100
Ethernet
MAC
xMII
Interface
Buffer
Manager
Clock
Adapters
SDRAM
Interface
Clock Inputs
Ordering Information
PART
PORTS TEMP RANGE PIN-PACKAGE
DS34S101GN*
1 -40°C to +85°C 256 TECSBGA
DS34S101GN+* 1 -40°C to +85°C 256 TECSBGA
DS34S102GN* 2 -40°C to +85°C 256 TECSBGA
DS34S102GN+* 2 -40°C to +85°C 256 TECSBGA
DS34S104GN
4 -40°C to +85°C 256 TECSBGA
DS34S104GN+
4 -40°C to +85°C 256 TECSBGA
DS34S108GN
8 -40°C to +85°C 484 HSBGA
DS34S108GN+ 8 -40°C to +85°C 484 HSBGA
+Denotes lead-free/RoHS-compliant package (explanation).
*Future product—contact factory for availability.
________________________________________________________ Maxim Integrated Products 1
Some revisions of this device may incorporate deviations from published specifications known as errata.
Multiple revisions of any device may be simultaneously available through various sales channels. For
information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering
information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.






DS34S101 Datasheet, Funktion
ABRIDGED DATA SHEET
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
www.DataSheet4U.com
4 Block Diagram
Figure 4-1. Top-Level Block Diagram
TDMn_ACLK
TDMn_TX
TDMn_TCLK
TDMn_TX_SYNC
TDM n_ TX_M F_CD
TDMn_ TSIG _CTS
TDMn_RCLK
TDMn_RX
TDMn_RX_SYNC
TDM n_RSIG _RTS
CLAD1
38 .88 M Hz
2.048 /1.544 MHz
Clock
Recovery
Machines
Timeslot
Assigner
TDMoP Block
all 8 ports
Payload Type
Machines
RAW
SAToP
SDRAM
Controller
CESoPSN
AAL 1
Jitter
Buffer
Control
HDLC
Packet
Classifier
CAS
Handler
Counters
& Status
Registers
Queue
Manager
CLAD2
50 or 75MHz
CLK_ SYS _S
CLK_ SYS
Ethernet
MAC
10/100
MII_TX_ERR
M II _TX_ EN
MII_TXD[3:0]
CLK_SSMII _TX
CLK_ M II_TX
MII_CRS
MII_COL
MII_RX_ERR
MII_RX_DV
M II_RXD[3 :0]
CLK_ M II_RX
MDIO
MDC
CPU
Interface
JTAG
SCAN
MBIST
Rev: 101708
6 of 13

6 Page









DS34S101 pdf, datenblatt
ABRIDGED DATA SHEET
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
www.DataSheet4U.com
8 Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
DS34S101, DS34S102 and DS34S108 have a 256-lead thermally enhanced chip-scale ball grid array (TECSBGA)
package. The TECSBGA package dimensions are shown in Maxim document 56-G6028-001.
DS34S108 has a 484-lead thermally enhanced ball grid array (TEBGA) package. The TEBGA package dimensions
are shown in Maxim document 56-G6038-001.
9 Thermal Information
Parameter
Target Ambient Temperature Range
Die Junction Temperature Range
Theta Jc (junction to top of case)
Theta Jb (junction to bottom pins)
Theta Ja, Still Air (Note 1)
TECSBGA-256
DS34S101
DS34S102
DS34S104
-40 to 85°C
-40 to 125°C
3.7 °C/W
13.1 °C/W
26.2 °C/W
TEBGA-484
DS34S108
-40 to 85°C
-40 to 125°C
4.2 °C/W
7.1 °C/W
16.1 °C/W
Note 1: These numbers are estimates using JEDEC standard PCB and enclosure dimensions.
Rev: 101708
12 of 13

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