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PDF DS2282 Data sheet ( Hoja de datos )
| Número de pieza | DS2282 | |
| Descripción | T1 FDL Controller/Monitor Stik | |
| Fabricantes | Dallas Semiconductor | |
| Logotipo |  |
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DS2282
DS2282
T1 FDL Controller/Monitor Stik
FEATURES
• Fully implements the FDL message format as de-
scribed in the ANSI document T1.403–1989
• Fully implements the maintenance message protocol
described in AT&T TR 54016 (1986/89)
• Provides high–level monitor counts, namely:
– Errored Seconds
– Severely Errored Seconds
– Unavailable Seconds
• Important counts are stored in nonvolatile memory
• Works in conjunction with the DS2283 Enhanced T1
Line Card Stik or DS2180A T1 Transceiver
• Simple serial port used to retrieve information and
control operation
• Can be used without an external controller
• Connects to a standard 30–pin Single In–Line con-
nector
• Single +5V supply
PIN ASSIGNMENT
VDD 1
RLOS 2
RCLK 3
RPOS 4
RNEG 5
NC 6
INT 7
PRMXA 8
DRVEN 9
RXD 10
TXD 11
TLCLK 12
SLIP 13
PLB 14
PAS 15
UB1 16
UB2 17
UB3 18
UB4 19
B8ZS 20
RST 21
NC 22
GND 23
UB5 24
UB6 25
LLB 26
PSEN 27
TLINK 28
NC 29
NC 30
(actual size)
DESCRIPTION
The DS2282 completely controls the Facility Data Link
(FDL) as described in the Bellcore document TR–
TSY–000194 (Extended Superframe Format Interface
Specification – December 1987) and the ANSI docu-
ment T1.403–1989 (Carrier to Carrier Installation – DS1
Metallic Interface). It also implements the protocol that
is described in the AT&T publication TR 54016 (Re-
quirements for Interfacing DTE to Services Employing
ESF – 1986/89). In addition it provides a number of im-
portant performance parameters involved in monitoring
T1 lines such as Errored Seconds, Severely Errored
Seconds, and Unavailable Seconds.
022798 1/22
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DS2282
PIN DESCRIPTION Table 1
PIN SYMBOL TYPE
1 VDD –
2 RLOS O
3 RCLK I
4 RPOS I
5 RNEG
6 NC –
7 INT O
8 PRMXA O
9 DRVEN O
10 RXD
I
11 TXD O
12 TLCLK
13 SLIP
I
I
14 PLB O
15 PAS
I
16 UB1
17 UB2
18 UB3
19 UB4
O
20 B8ZS
I
21 RST
I
DESCRIPTION
Positive Supply. 5.0 volts.
Receive Loss Of Sync. Indicates sync status; high when internal resync
is in progress, low otherwise.
Receive Clock. 1.544 MHz clock input. All internal time intervals are
derived from this clock. A clock must be applied to this pin or the DS2282
will not operate properly.
Receive Bipolar Data. Sampled on falling edge of RCLK. Can be tied
together to receive NRZ data and disable BPV and B8ZS detection circuit-
ry.
No Connect. Do not connect any signal to this pin.
Interrupt. Transitions low when bits in the Status Register (SR) change
state or when an unscheduled message (T1.403) or request message
(54016) is received.
PRM Transmit Active. Transitions high when a Performance Report
Message (T1.403) or response message (54016) is being sent via TLINK.
DS2282 will transmit 27 flags before each messages. The PRMXA pin will
be high for the message and flags.
Serial Port Drive Enable. Driven high when the DS2282 is transmitting
data via TXD. Can be used to enable an external line driver. Tie this pin
low to invoke 8–bit communications via the serial port.
Serial Port Receive. Serial data input; data is input asynchronously at
19.2Kbps.
Serial Port Transmit. Serial data output; data is output asynchronously
at 19.2Kbps.
Transmit Link Clock. 4 KHz demand clock for the FDL data.
Slip Occurrence Event. This edge–triggered pin should be held low for
at least 10 µs when a slip occurs locally. If local slip indications are not
available, this pin should be tied low to allow model #3 to be sent in 54016
mode.
Payload Loopback. Transitions high when the code word or message for
payload loopback activate has been received; transitions low when the
code word or message for payload loopback deactivate has been re-
ceived.
Program Address Select. Used to program the serial port address; ac-
tive high.
User Bits 1 to 4. Each user bit can be independently configured either
high or low via the UBR register. In hardware mode, tied high or low exter-
nally to configure DS2282.
B8ZS Enable. Tie low to disable B8ZS; tie high to enable B8ZS. Logically
OR’ed with the B8ZS bit in the UBR register; tie low if the B8ZS bit is to be
used to select B8ZS mode.
Reset. Active high level will initiate a reset. Contains an internal pull–
down resister.
022798 5/22
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DS2282
NAME
ADDR2,3 R/W CLEARABLE DESCRIPTION
UASICR
29 R
No UAS Interval Count Registers. A set of 96 16–bit registers
that contain the Unavailable Second counts for the previous
96 individual 15–minute periods. Most recent interval is read
first.
BESICR
2A R
No BES Interval Count Registers. A set of 96 16–bit registers
that contain the Bursty Errored Second counts for the pre-
vious 96 individual 15–minute periods. Most recent interval
is read first.
SESICR
2B R
No SES Interval Count Registers. A set of 96 16–bit registers
that contain the Severely Errored Second counts for the pre-
vious 96 individual 15–minute periods. Most recent interval
is read first.
CSLFICR
2C
R
No CSS & LOFC Interval Count Registers. A set of 96 16–bit
registers that contain the Controlled Slip and Loss Of Frame
counts for the previous 96 individual 15–minute periods. The
8–bit CSS count is the LSB and the 8–bit LOFC count is in
the MSB. Most recent interval is read first.
ESDCR
2D R
No ES Day Count Registers. A 16–bit register that counts the
number of Errored Seconds in the previous 24–hour period.
UEEER
36 R
Yes User ESF Error Event Register. 16–bit register that mimics
the ESFEER for user access.
UASDCR
2E
R
No UAS Day Count Registers. A 16–bit register that counts
the number of Unavailable Seconds in the previous 24–hour
period.
BESDCR
2F
R
No BES Day Count Registers. A 16–bit register that counts
the number of Bursty Errored Seconds in the previous
24–hour period.
SESDCR
30
R
No SES Day Count Registers. A 16–bit register that counts the
number of Severely Errored Seconds in the previous
24–hour period.
CSLFDCR
31
R
No CSS & LOFC Day Count Registers. A 16–bit register that
counts the number of Controlled Slip Seconds and Loss Of
Frames in the previous 24–hour period. The 8–bit CSS
count is in the LSB and the 8–bit LOFC count is in the MSB.
VITR
32 R
No Valid Interval Total Register. An 8–bit register that indi-
cates the number of valid 15–minute intervals in the previous
24–hour period.
RMSR
33 R
Yes Request Message Status Register. An 8–bit register that
indicates which (if any) request message is being received.
CR
34 W
No Control Register. An 8–bit register that selects which ad-
dress the DS2282 will respond to.
NOTES:
1. All of the registers in the DS2282 that count events will saturate at their maximum possible count; they do not
roll over. For example, all the 16–bit registers stop at a count of 65,535. They do not roll over to zero and
continue counting.
2. Values indicated in hexadecimal format.
3. All register read/written LSB first.
022798 11/22
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