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W9864G6GH Schematic ( PDF Datasheet ) - Winbond

Teilenummer W9864G6GH
Beschreibung 1M X 4 BANKS X 16 BITS SDRAM
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W9864G6GH Datasheet, Funktion
www.DataSheet4U.com
W9864G6GH
1M × 4 BANKS × 16 BITS SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. AVAILABLE PART NUMBER ..................................................................................................... 4
4. PIN CONFIGURATION ............................................................................................................... 4
5. PIN DESCRIPTION..................................................................................................................... 5
6. BLOCK DIAGRAM ...................................................................................................................... 6
7. FUNCTIONAL DESCRIPTION ................................................................................................... 7
7.1 Power Up and Initialization ............................................................................................. 7
7.2 Programming Mode Register Set command .................................................................. 7
7.3 Bank Activate Command ................................................................................................ 7
7.4 Read and Write Access Modes ...................................................................................... 7
7.5 Burst Read Command .................................................................................................... 8
7.6 Burst Command.............................................................................................................. 8
7.7 Read Interrupted by a Read ........................................................................................... 8
7.8 Read Interrupted by a Write............................................................................................ 8
7.9 Write Interrupted by a Write............................................................................................ 8
7.10 Write Interrupted by a Read............................................................................................ 8
7.11 Burst Stop Command ..................................................................................................... 9
7.12 Addressing Sequence of Sequential Mode .................................................................... 9
7.13 Addressing Sequence of Interleave Mode ..................................................................... 9
7.14 Auto-precharge Command ........................................................................................... 10
7.15 Precharge Command.................................................................................................... 10
7.16 Self Refresh Command ................................................................................................ 10
7.17 Power Down Mode ....................................................................................................... 11
7.18 No Operation Command............................................................................................... 11
7.19 Deselect Command ...................................................................................................... 11
7.20 Clock Suspend Mode.................................................................................................... 11
8. OPERATION MODE ................................................................................................................. 12
9. ELECTRICAL CHARACTERISTICS......................................................................................... 13
9.1 Absolute Maximum Ratings .......................................................................................... 13
9.2 Recommended DC Operating Conditions .................................................................... 13
Publication Release Date:Aug. 13, 2007
- 1 - Revision A09






W9864G6GH Datasheet, Funktion
www.DataSheet4U.com
6. BLOCK DIAGRAM
W9864G6GH
CLK
CKE
CS
RAS
CAS
WE
CLOCK
BUFFER
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
A10
A0 MODE
REGISTER
A9 ADDRESS
A11 BUFFER
BS0
BS1
REFRESH
COUNTER
COLUMN
COUNTER
COLUMN DECODER
CELL ARRAY
BANK #0
SENSE AMPLIFIER
DATA CONTROL
CIRCUIT
COLUMN DECODER
CELL ARRAY
BANK #2
SENSE AMPLIFIER
COLUMN DECODER
CELL ARRAY
BANK #1
SENSE AMPLIFIER
DQ
BUFFER
COLUMN DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
DQ0
DQ15
UDQM
LDQM
NOTE:
The cell array configuration is 4096 * 256 * 16
Publication Release Date:Aug. 13, 2007
- 6 - Revision A09

6 Page









W9864G6GH pdf, datenblatt
www.DataSheet4U.com
W9864G6GH
8. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
Table 1 Truth Table (note (1), (2))
Command
Device
State
A0-A9,
CKEn-1 CKEn DQM BS0, 1 A10
CS
A11
Bank Active
Idle H x x v v V L
Bank Precharge
Any H x x v L x L
Precharge All
Any H x x x H x L
Write
Active (3) H x x v L v L
Write with Auto-precharge Active (3) H x x v H v L
Read
Active (3) H x x v L v L
Read with Auto-precharge Active (3) H x x v H v L
Mode Register Set
Idle H x x v v v L
No-Operation
Any H x x x x x L
Burst Stop
Active (4) H x x x x x L
Device Deselect
Any H x x x x x H
Auto-Refresh
Idle H H x x x x L
Self-Refresh Entry
Idle H L x x x x L
Self Refresh Exit
idle
(S.R)
L Hx x x xH
L Hx x x xL
Clock suspend Mode
Entry
Active
H Lxxxxx
Idle H L x x x x H
Power Down Mode Entry
Active (5) H L x x x x L
Clock Suspend Mode Exit Active
L Hx x x x x
Power Down Mode Exit
Any
(power
down)
L Hx x x xH
L Hx x x xL
Data write/Output Enable
Active
H xLxxxx
Data write/Output Disable Active H x H x x x x
Notes:
(1) v = valid, x = Don't care, L = Low Level, H = High Level
(2) CKEn signal is input leve l when commands are provided.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
RAS CAS WE
L HH
L HL
L HL
H LL
H LL
H LH
H LH
L LL
H HH
H HL
x xx
L LH
L LH
x xx
H Hx
x xx
x xX
H HH
x xX
x xX
H HH
x xx
x xx
- 12 -
Publication Release Date:Aug. 13, 2007
Revision A09

12 Page





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