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ADC11DL066 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC11DL066
Beschreibung 450 MHz Input Bandwidth A/D Converter w/Internal Reference
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 23 Seiten
ADC11DL066 Datasheet, Funktion
www.DataSheet4U.com
March 2004
ADC11DL066
Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D
Converter w/Internal Reference
General Description
The ADC11DL066 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog in-
put signals into 11-bit digital words at 66 Megasamples per
second (MSPS), minimum. This converter uses a differential,
pipeline architecture with digital error correction and an on-
chip sample-and-hold circuit to minimize die size and power
consumption while providing excellent dynamic performance
and a 450 MHz Full Power Bandwidth. Operating on a single
3.3V power supply, the ADC11DL066 achieves 10.3 effective
bits and consumes just 686 mW at 66 MSPS, including the
reference current. The Power Down feature reduces power
consumption to 75 mW.
The differential inputs provide a full scale differential input
swing equal to 2 times VREF with the possibility of a single-
ended input. Full use of the differential input is recom-
mended for optimum performance. The digital outputs from
the two ADCs are available on separate 11-bit buses with an
output data format choice of offset binary or two’s comple-
ment.
To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC11DL066 can be con-
nected to a separate supply voltage in the range of 2.4V to
the digital supply voltage.
This device is available in the 64-lead TQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C. An evaluation board is available to ease the evalua-
tion process.
Features
n Single +3.3V supply operation
n Internal sample-and-hold
n Outputs 2.4V to 3.3V compatible
n Power down mode
n On-chip reference
Key Specifications
n Resolution
n DNL
n SNR (fIN = 10 MHz)
n SFDR (fIN = 10 MHz)
n Data Latency
n Power Consumption
— Operating
— Power Down
Applications
n Ultrasound and Imaging
n Instrumentation
n Communications Receivers
n Sonar/Radar
n xDSL
n Cable Modems
n DSP Front Ends
11 Bits
±0.25 LSB (typ)
64 dB (typ)
80 dB (typ)
6 Clock Cycles
686 mW (typ)
75 mW (typ)
Connection Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation DS200773
20077301
20040326
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ADC11DL066 Datasheet, Funktion
Converter Electrical Characteristics (Continued)
www.DataSheet4U.com
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V,
VDR = +2.5V, PD = 0V, INT/EXT REF pin = +3.3V, VREF = +1.0V, fCLK = 66 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin.
Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical Limits
(Note 10) (Note 10)
Units
(Limits)
DYNAMIC CONVERTER CHARACTERISTICS
FPBW Full Power Bandwidth
0 dBFS Input, Output at −3 dB
450
MHz
SNR
Signal-to-Noise Ratio
SINAD Signal-to-Noise and Distortion
ENOB Effective Number of Bits
THD
Total Harmonic Distortion
H2 Second Harmonic
H3 Third Harmonic
SFDR Spurious Free Dynamic Range
INTER-CHANNEL CHARACTERISTICS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 33 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 33 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0,5 dBFS
fIN = 33 MHz, VIN = −0,5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 33 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 33 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 33 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 33 MHz, VIN = −0.5 dBFS
64
64
62
63
63
62
10.3
10.3
10.1
−78
−78
−78
−84
−84
−84
−84
−84
−83
80
80
74
62
62
10.0
-69.7
−73.5
−73.3
73.5
dB
dB (min)
dB
dB
dB (min)
dB
Bits
Bits (min)
Bits
dB
dB (max)
dB
dB
dB (max)
dB
dB
dB (max)
dB
dB
dB (min)
dB
Channel — Channel Offset Match
±0.03
%FS
Channel — Channel Channel gain
Match
±0.1
%FS
Crosstalk
10 MHz Tested, Channel;
20 MHz Other Channel
10 MHz Tested, Channel;
195 MHz Other Channel
80
63
dB
dB
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ADC11DL066 pdf, datenblatt
Typical Performance Characteristics VA = VD = +3.3V, VDR = +2.5V, fCLK = 66 MHz, fIN = 10 MHz
www.DataSheuent4leUss.coothmerwise stated (Continued)
INL vs. fCLK
INL vs. Clock Duty Cycle
INL vs. VDR
20077324
INL vs. Temperature
20077325
20077326
SNR, SINAD, SFDR vs. fCLK
20077327
SNR, SINAD, SFDR vs. CLOCK DUTY CYCLE
www.national.com
20077328
12
20077329

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