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PDF NJU7380 Data sheet ( Hoja de datos )
| Número de pieza | NJU7380 | |
| Descripción | Stepper Motor / EMP14 | |
| Fabricantes | JRC | |
| Logotipo |  |
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STEPPER MOTOR CONTROLLER
NJU7380
s GENERAL DESCRIPTION
NJU7380 is a controller with transrator which convert
from input step and direction pulse to driver's phase signal
for full and half step.
NJU7380 translates from pulse input signal (Serial
interface) to phase signal input, so NJM3700 series dual
channel bipolar drivers or NJM2672 dual H-bridge driver
can be easily controlled by a micro processor .
NJU7380 is also including Auto Current Down (ACD)
circuit which is suitable for reducing power dissipation of
power devices and motor.
s PACKAGE OUTLINE
NJU7380E
s FEATURES
• Operating Voltage VDD=4.75 ∼ 5.25V
• Absolute Maximum Voltage 7V
• Half -step and Full - step Operation
• Internal Phase Logic
• Phase Logic Reset Terminal(RESET)
• Internal Auto Current Down Function
• Specially matched to NJM3775,NJM3777 and NJM2672.
• C-MOS Technology
• Package Outline EMP14
s PIN CONFIGURATIONS
1
2
3
4
5
6
7
14
1. DIR
8. MO
13 2. STEP 9. ACD
3. HSM 10. Dis2
12
4. RESET 11. Dis1
11 5. Ct 12. PB
6. SGND 13. PA
10 7. PGND 14. VDD
9
8
Fig. 1Pin Configurations
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NJU7380
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• HSM – half/full step mode switching
This signal determines whether the stepping motor turns at half step or full step mode. The built-in phase
logic is set to the half step mode when HSM is low level. Although HSM can be modified this should be
avoided since a misstep of 1 pulse increment may occur if it is set simultaneous with the negative edge. See
the timing chart in Figure 4.
• RESET
A two-phase stepping motor repeats the same winding energizing sequence every angle that is a multiple of
four of the basic step. The phase logic sequence is repeated every four pulses in the full step mode and every
eight pulses in the half step mode.
RESET forces to initialize the phase logic to sequence start mode.
When RESET is at L level, the phase logic is initialized and the energizing pattern of phase logic at
sequence start is output. At this time, the STEP input of phase logic will be ignored during the RESET is at
level.
s POR – power on and reset function
The internal power-on and reset circuit, which is connected to Vcc, resets the phase logic and turns off phase
output when the power is supplied to prevent missteps.
Each time the power is turned on, the energizing pattern of phase logic at sequence start is output.
s MO – origin monitor
At sequence start of the phase logic or after POR or external RESET, an L level output is made to indicate to
external devices that the energizing sequence is in initial status.
In a system using a stepping motor, the device sensor and the MO AND function enable a higher resolution
detection of motor origin.
HSM,DIR
STEP,RESET
Vp
ts tp
td
Fig.4 Timing chart
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5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet NJU7380.PDF ] | |
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