ADN4667 Datasheet PDF - Analog Devices
| Part Number | ADN4667 | |
| Description | 3V LVDS Quad CMOS Differential Line Driver | |
| Manufacturers | Analog Devices | |
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FEATURES
±15 kV ESD protection on output pins
400 Mbps (200 MHz) switching rates
Flow-through pinout simplifies PCB layout
300 ps typical differential skew
400 ps maximum differential skew
1.7 ns maximum propagation delay
3.3 V power supply
±310 mV differential signaling
Low power dissipation (10 mW typical)
Interoperable with existing 5 V LVDS receivers
High impedance on LVDS outputs on power-down
Conforms to TIA/EIA-644 LVDS standard
Industrial operating temperature range: −40°C to +85°C
Available in low profile TSSOP package
APPLICATIONS
Backplane data transmission
Cable data transmission
Clock distribution
GENERAL DESCRIPTION
The ADN4667 is a quad, CMOS, low voltage differential
signaling (LVDS) line driver offering data rates of over
400 Mbps (200 MHz) and ultralow power consumption.
It features a flow-through pinout for easy PCB layout and
separation of input and output signals.
The device accepts low voltage TTL/CMOS logic signals and
converts them to a differential current output of typically ±3.1 mA
for driving a transmission medium such as a twisted pair cable.
The transmitted signal develops a differential voltage of typi-
cally ±310 mV across a termination resistor at the receiving end.
This is converted back to a TTL/CMOS logic level by an LVDS
receiver.
3 V LVDS Quad CMOS
Differential Line Driver
ADN4667
FUNCTIONAL BLOCK DIAGRAM
VCC
ADN4667
DIN1
D1
DOUT1+
DOUT1–
DIN2
DOUT2+
D2
DOUT2–
DIN3
DOUT3+
D3
DOUT3–
DIN4
EN
EN
DOUT4+
D4
DOUT4–
GND
Figure 1.
The ADN4667 also offers active high and active low enable/
disable inputs (EN and EN). These inputs control all four
drivers and turn off the current outputs in the disabled state to
reduce the quiescent power consumption to typically 10 mW.
The ADN4667 and a companion LVDS receiver offer a new
solution to high speed, point-to-point data transmission, and a
low power alternative to emitter-coupled logic (ECL) or positive
emitter-coupled logic (PECL).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
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TEST CIRCUITS
VCC
DIN
DOUT+
RL/2
RL/2
V VOS V VOD
DRIVER IS ENABLED
DOUT–
Figure 2. Test Circuit for Driver VOD and VOS
DIN
DOUT–
DOUT+
tPLHD
VOD
ADN4667
SIGNAL
GENERATOR
VCC
DIN
50Ω
CL
CL
DOUT+
DOUT–
DRIVER IS
ENABLED
NOTES
1. CL INCLUDES LOAD AND TEST JIG CAPACITANCE.
Figure 3. Test Circuit for Driver Propagation Delay and Transition Time
tPHLD
3V
1.5V
0V
VOH
0V (DIFFERENTIAL)
VOL
VDIFF
VDIFF = DOUT+ – DOUT–
80%
0V
20%
tTLH
tTHL
Figure 4. Driver Propagation Delay and Transition Time Waveforms
VCC
DIN
SIGNAL
GENERATOR
50Ω
EN
EN
CL 50Ω
50Ω
CL
DOUT+
1.2V
DOUT–
Figure 5. Test Circuit for Driver Three-State Delay
EN WITH EN = GND
OR OPEN-CIRCUIT
EN WITH EN = VCC
DOUT+ WITH DIN = VCC
OR DOUT– WITH DIN = GND
DOUT+ WITH DIN = GND
OR DOUT– WITH DIN = VCC
tPHZ
tPLZ
tPZH
tPZL
3V
1.5V
0V
3V
1.5V
0V
VOH
50%
1.2V
1.2V
50%
VOL
Figure 6. Driver Three-State Delay Waveforms
Rev. 0 | Page 5 of 12
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for ADN4667 electronic component. |
| Information | Total 12 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ ADN4667.PDF Datasheet ] | |
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