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ADJD-S371-QR999 Schematic ( PDF Datasheet ) - AVAGO TECHNOLOGIES LIMITED

Teilenummer ADJD-S371-QR999
Beschreibung Miniature Surface-Mount RGB Digital Color Sensor Module
Hersteller AVAGO TECHNOLOGIES LIMITED
Logo AVAGO TECHNOLOGIES LIMITED Logo 




Gesamt 23 Seiten
ADJD-S371-QR999 Datasheet, Funktion
www.DataSheet4U.com
ADJD-S371-QR999
Miniature Surface-Mount
RGB Digital Color Sensor Module
Data Sheet
Description
ADJD-S371-QR999 is a cost effective, 4 channel digital
output RGB+CLEAR sensor in miniature surface-mount
package with a mere size of 3.9 x 4.5 x 1.8 mm. It is
an IC module with combination of White LED and
CMOS IC with integrated RGB filters + Clear channel and
analog-to-digital converter front end.
It is ideal for applications like color detection, mea-
surement, illumination sensing for display backlight
adjustment such as colors, contrast and brightness
enhancement in mobile devices which demand higher
package integration, small footprint and low power
consumption.
The 2-wire serial output allows direct interface to
microcontroller or other logic control for further signal
processing without additional component such as
analog to digital converter. With the wide sensing
range of 100 lux to 100,000 lux, the sensor can be used
for many applications with different light levels by
adjusting the gain setting. Additional features include
a selectable sleep mode to minimize current con-
sumption when the sensor is not in use.
Features
Four channel integrated light to digital converter
(Red, Green, Blue and Clear).
10 bit digital output resolution
Independent gain selection for each channel
Wide sensitivity coverage: 0.1 klux - 100 klux
Two wire serial communication
Built in oscillator/selectable external clock
Low power mode (sleep mode)
Small 3.9 x 4.5 x 1.8 mm module
Integrated solution with sensor, LED and separator
in module for ease of design
Lead free
Applications
Mobile appliances
Consumer appliances







ADJD-S371-QR999 Datasheet, Funktion
www.DataSheet4U.com
Serial Interface Timing Information
Parameter
SCL Clock Frequency
(Repeated) START Condition Hold Time
Data Hold Time
SCL Clock Low Period
SCL Clock High Period
Repeated START Condition Setup Time
Data Setup Time
STOP Condition Setup Time
Bus Free Time Between START and STOP Conditions
Symbol
fscl
tHD:STA
tHD:CAT
tLOW
tHIGH
tSU:STA
tSU:DAT
tSU:STD
tBUF
Minimum
0
4
0
4.7
4.0
4.7
250
4.0
4.7
Maximum
100
-
3.45
-
-
-
-
-
-
Units
kHz
µs
µs
µs
µs
µs
µs
µs
µs
SDA
tHD:STA
tHIGH
tSU:DAT
SCL
S
tLOW
tHD:DAT
Figure 2. Serial interface bus timing waveforms
tSU:STA
tBUF
Sr
tHD:STA
P
tSU:STO
S
Serial Interface Reference
Description
The programming interface to the ADJD-S371-QR999 is
a 2-wire serial bus. The bus consists of a serial clock (SCL)
and a serial data (SDA) line. The SDA line is bi-directional
on ADJD-S371-QR999 and must be connected through
a pull-up resistor to the positive power supply. When the
bus is free, both lines are HIGH.
The 2-wire serial bus on ADJD-S371-QR999 requires one
device to act as a master while all other devices must be
slaves. A master is a device that initiates a data transfer
on the bus, generates the clock signal and terminates
the data transfer while a device addressed by the master
is called a slave. Slaves are identified by unique device
addresses.
Both master and slave can act as a transmitter or a
receiver but the master controls the direction for data
transfer. A transmitter is a device that sends data to the
bus and a receiver is a device that receives data from
the bus.
The ADJD-S371-QR999 serial bus interface always oper-
ates as a slave transceiver with a data transfer rate of up
to 100kbit/s.
START/STOP Condition
The master initiates and terminates all serial data
transfers. To begin a serial data transfer, the master must
send a unique signal to the bus called a START condition.
This is defined as a HIGH to LOW transition on the SDA
line while SCL is HIGH.


6 Page









ADJD-S371-QR999 pdf, datenblatt
www.DataSheet4U.com
Mechanical Drawing
4.50
SENSOR
PCB
LIGHT SEPARATOR
LED
A
3.90
A
1.80
SECTION A - A
LED PAD
(AT TOP SIDE)
BOTTOM SIDE
12
1
2
3
4
11 10
9
8
5 67
ORIENTATION MARK
0.80
TOP SIDE
(LED AREA)
12
1
2
3
4
FOOTPRINT AT BOTTOM SIDE
Pin Name
Description
1
LED -VE
LED cathode
2 NC
No connection
3 LED +VE LED anode
4 SDA
Bidirectional data pin. A pull-up resistor should be tied to SDA because it goes tri-state to
output logic 1
5 DVDD Digital power pin
6 SCL
Serial interface clock
7 AVDD Analog power pin
8 SLEEP Sleep pin. When SLEEP = 1, the device goes into sleep mode. In sleep mode, all analog circuits
are powered down and the clock signal is gated away from the core logic resulting in very low
current consumption.
9 AGND Analog ground pin
10 XRST
Reset pin. Global, asynchronous, active-low system reset. When asserted low, XRST resets all
registers. Minimum reset pulse low is 1us and must be provided by external circuitry.
11 DGND
Digital ground pin
12 XCLK
External clock input
12

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