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PDF ADJD-S313-QR999 Data sheet ( Hoja de datos )
| Número de pieza | ADJD-S313-QR999 | |
| Descripción | Miniature Surface Mount RGB Digital Color Sensor | |
| Fabricantes | AVAGO TECHNOLOGIES LIMITED | |
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ADJD-S313-QR999
Miniature Surface-Mount RGB Digital Color Sensor
Data Sheet
Description
The ADJD-S313-QR999 is a cost effective, CMOS
digital output RGB color sensor in miniature
surface-mount package with a mere size of
5x5x0.75mm. The IC comes with integrated RGB
filters, an analog-to-digital converter and a digital
core for communication and sensitivity control. The
output allows direct interface to micro-controller
or other logic control for further signal processing
without the need of any additional components.
This device is designed to cater for wide dynamic
range of illumination level and is ideal for
applications like portable or mobile devices which
demand higher integration, smaller size and low
power consumption. Sensitivity control is
performed by the serial interface and can be
optimized individually for the different color
channel. The sensor can also be used in conjunction
with a white LED for reflective color management.
General Specifications
Feature Value
Interface 100kHz serial interface
Supply 2.6V digital (nominal), 2.6V analog (nominal)
Features
• Fully integrated RGB digital color sensor
• Digital I/O via 2-wire serial interface
• Industry’s smallest form factor – QFN 5x5x0.75mm
• Adjustable sensitivity for different levels of
illumination
• Uniformly distributed RGB photodiode array
• 7 bit resolution per channel output
• Built in internal oscillator
• Sleep function when not in use
• No external components
• Low supply voltage (VDD) 2.6V
• 0°C to 70°C operating temperature
• Lead free package
Applications
• General color detection and measurement
• Mobile appliances such as mobile phones, PDAs,
MP3 players,etc.
• Consumer appliances
• Portable medical equipments
• Portable color detector/reader
ESD WARNING: Standard CMOS handling precautions should be observed to avoid static discharge.
AVAGO TECHNOLOGIES' PRODUCTS AND SOFTWARE ARE NOT SPECIFICALLY DESIGNED, MANUFACTURED OR AUTHORIZED FOR SALE AS
PARTS, COMPONENTS OR ASSEMBLIES FOR THE PLANNING, CONSTRUCTION, MAINTENANCE OR DIRECT OPERATION OF A NUCLEAR FACILITY
OR FOR USE IN MEDICAL DEVICES OR APPLICATIONS. CUSTOMER IS SOLELY RESPONSIBLE, AND WAIVES ALL RIGHTS TO MAKE CLAIMS
AGAINST AVAGO TECHNOLOGIES OR ITS SUPPLIERS, FOR ALL LOSS, DAMAGE, EXPENSE OR LIABILITY IN CONNECTION WITH SUCH USE.
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Notes:
1. The “Absolute Maximum Ratings” are those values beyond which
damage to the device may occur. The device should not be
operated at these limits. The parametric values defined in the
“Electrical Specifications” table are not guaranteed at the absolute
maximum ratings. The “Recommended Operating Conditions”
table will define the conditions for actual device operation.
2. Unless otherwise specified, all voltages are referenced to ground.
3. Specified at room temperature (25°C) and VDDD = VDDA = 2.6V.
4. Applies to all DI pins.
5. Applies to all DO pins. SDASLV go tri-state when output logic
high. Minimum VOH depends on the pull-up resistor value.
6. Applies to all DO and DIO pins.
7. Dynamic testing is performed with the IC operating in a mode
representative of typical operation.
8. Refers to total device current consumption.
9. Output and bidirectional pins are not loaded.
10. Test condition is blue light of peak wavelength (λP) 460 nm and
spectral half width (∆λ½) 25 nm.
11. Test condition is green light of peak wavelength (λP) 542 nm and
spectral half width (∆λ½) 35 nm
12. Test condition is red light of peak wavelength (λP) 645 nm and
spectral half width (∆λ½) 20 nm
13. Saturation irradiance = (MSB)/(Irradiance responsivity)
Spectral response
1
0.8
0.6
0.4
0.2
0
400
500 600
Wavelength (nm)
700
Typical spectral response when the gains for all the
color channels are set at equal.
Serial Interface Timing Information
Parameter
SCL clock frequency
(Repeated) START condition hold time
Data hold time
SCL clock low period
SCL clock high period
Repeated START condition setup time
Data setup time
STOP condition setup time
Bus free time between START and STOP conditions
tHD:STA
SDA
tHIGH
tSU:DAT
SCL
S
tLOW
tHD:DAT
Figure 1. Serial Interface Bus Timing Waveforms
5
Symbol
fscl
tHD:STA
tHD:DAT
tLOW
tHIGH
tSU:STA
tSU:DAT
tSU:STO
tBUF
Minimum
0
4
0
4.7
4.0
4.7
250
4.0
4.7
Maximum
100
-
3.45
-
-
-
-
-
-
Units
kHz
µs
µs
µs
µs
µs
ns
µs
µs
tSU:STA
tBUF
Sr
tHD:STA
P
tSU:STO
S
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Data format
ADJD-S313 uses a register-based programming
architecture. Each register has a unique address and
controls a specific function inside the chip.
To write to a register, the master first generates a
START condition. Then it sends the slave address
for the device it wants to communicate with. The
least significant bit (LSB) of the slave address must
indicate that the master wants to write to the slave.
The addressed device will then acknowledge the
master.
The master writes the register address it wants to
access and waits for the slave to acknowledge. The
master then writes the new register data. Once the
slave acknowledges, the master generates a STOP
condition to end the data transfer.
To read from a register, the master first generates
a START condition. Then it sends the slave address
for the device it wants to communicate with. The
least significant bit (LSB) of the slave address must
indicate that the master wants to write to the slave.
The addressed device will then acknowledge the
master.
The master writes the register address it wants to
access and waits for the slave to acknowledge. The
master then generates a repeated START condition
and resends the slave address sent previously. The
least significant bit (LSB) of the slave address must
indicate that the master wants to read from the
slave. The addressed device will then acknowledge
the master.
The master reads the register data sent by the slave
and sends a no acknowledge signal to stop reading.
The master then generates a STOP condition to end
the data transfer.
Start condition
Master will write data
Stop condition
S A6 A5 A4 A3 A2 A1 A0 W A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A P
Master sends
slave address
Master writes
register address
Master writes
register data
Slave acknowledge
Slave acknowledge
Slave acknowledge
Figure 8. Register Byte Write Protocol
Start condition
Master will write data
Repeated start
condition
Master will read data
Stop condition
S A6 A5 A4 A3 A2 A1 A0 W A D7 D6 D5 D4 D3 D2 D1 D0 A Sr A6 A5 A4 A3 A2 A1 A0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P
Master sends
slave address
Master writes
register address
Master sends
slave address
Master reads
register data
Slave acknowledge
Slave acknowledge
Slave acknowledge
Master not
acknowledge
Figure 9. Register Byte Read Protocol
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