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DC89C386 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DC89C386
Beschreibung Twelve Channel CMOS Differential Line Receiver
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 10 Seiten
DC89C386 Datasheet, Funktion
October 2001
DS89C386
Twelve Channel CMOS Differential Line Receiver
www.datashGeete4un.ceomral Description
The DS89C386 is a high speed twelve channel CMOS dif-
ferential receiver that meets the requirements of TIA/EIA-
422-B. The DS89C386 features low power dissipation of 240
mW typical.
Each TRI-STATE® enable, EN, allows the receiver output to
be active or in a Hi-impedance off state. Each enable is
common to only two receivers for flexibility and multiplexing
of receiver outputs.
The receiver output (RO) is guaranteed to be High when the
inputs are left open and unterminated. The receiver can
detect signals as low and including ±200 mV over the com-
mon mode range of ±7V. The receiver outputs (RO) are
compatible with both TTL and CMOS levels.
Features
n Low power design — 240 mW typical
n Meets TIA/EIA-422-B (RS-422)
n Receiver OPEN input failsafe feature
n Guaranteed AC parameters:
— Maximum receiver skew −4 ns
— Maximum transition time −9 ns
n High Output Drive Capability: ±6 mA
n Available in SSOP packaging:
— Requires 30% less PCB space than 3 DS34C86TMs
Connection Diagram
48L SSOP
DS89C386
Function Diagram
1/6 of package
01208502
Truth Table
Enable
Inputs
EN RI–RI*
LX
H 200 mV or OPEN
H −200 mV
H +200 mV > and > −200 mV
Not terminated.
Output
RO
Z
H
L
X
01208501
Order Number DS89C386TMEA
See NS Package Number MS48A
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation DS012085
www.national.com






DC89C386 Datasheet, Funktion
Application Information (Continued)
gation delay measurements (see Figures 5, 6). Differential
skew is calculated from tPHLD and tPLHD differential propa-
gation delay measurements (see Figures 7, 8).
(Circuit 1)
www.datasheet4u.com
01208508
(Circuit 2)
01208509
FIGURE 5. Circuits for Measuring Single-Ended Propagation Delays (See Figure 6)
Waveforms for Circuit 1
Waveforms for Circuit 2
01208510
FIGURE 6. Propagation Delay Waveforms for Circuit 1 and Circuit 2 (See Figure 5)
In Figure 6, VX, where X is a number, is the waveform
voltage level at which the propagation delay measurement
either starts or stops. Furthermore, V1 and V2 are normally
identical. The same is true for V3 and V4. However, as
mentioned before, these levels are not standardized and
may vary, even with similar devices from other companies.
Also note, VREF in Figure 1 should equal V1 and V2 in Figure
6.
The single-ended skew provides information about the pulse
width distortion of the output waveform. The lower the skew,
the less the output waveform will be distorted. For best case,
skew would be zero, and the output duty cycle would be
50%, assuming the input has a 50% duty cycle.
Waveforms for Circuit 3
(Circuit 3)
01208511
01208512
FIGURE 7. Circuit for Measuring Differential
Propagation Delays (See Figure 8)
www.national.com
01208513
FIGURE 8. Propagation Delay Waveforms
for Circuit 3 (see Figure 7)
For differential propagation delays, V1 may not equal V2.
Furthermore, the crossing point of RI and RI* corresponds to
zero volts on the differential waveform. (See middle wave-
form in Figure 8.) This is true whether V1 equals V2 or not.
However, if V1 and V2 are specified voltages, then V1 and
6

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