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PDF A4940 Data sheet ( Hoja de datos )
| Número de pieza | A4940 | |
| Descripción | Automotive Full Bridge MOSFET Driver | |
| Fabricantes | Allegro Micro Systems | |
| Logotipo |  |
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A4940
Automotive Full Bridge MOSFET Driver
Features and Benefits
www.da▪taHsihgehetc4uur.creonmt gate drive for N-channel MOSFET full bridge
▪ Independent control of each MOSFET
▪ Charge pump for low supply voltage operation
▪ Cross-conduction protection with adjustable dead time
▪ 5.5 to 50 V supply voltage range
▪ Diagnostics output
▪ Low current sleep mode
Package: 24-pin TSSOP with exposed
thermal pad (suffix LP)
Not to scale
Description
The A4940 is a full-bridge controller for use with external
N-channel power MOSFETs and is specifically designed for
automotive applications with high-power inductive loads such
as brush DC motors.
A unique charge pump regulator provides full ( >10 V ) gate
drive for battery voltages down to 7 V and allows the A4940
to operate with a reduced gate drive, down to 5.5 V.
A bootstrap capacitor is used to provide the above battery
supply voltage required for N-channel MOSFETs. A unique
bootstrap charge management system ensures that the bootstrap
capacitor is always sufficiently charged to supply the high-side
gate drive circuit.
Each of the power MOSFETs is controlled independently but
all are protected from shoot-through by dead time that is user-
configured by an external resistor.
Integrated diagnostics provide indication of undervoltage and
overtemperature faults.
The A4940 is supplied in a 24-pin TSSOP power package with
an exposed pad for enhanced thermal dissipation (package
type LP). It is lead (Pb) free, with 100% matte tin leadframe
plating (suffix –T).
A4940-DS
FAULT
AHI
BHI
ALO
BLO
Typical Application
A4940
VBAT
M
1 page  
A4940
Automotive Full Bridge MOSFET Driver
www.datasheet4u.com
ELECTRICAL CHARACTERISTICS
(continued)
Valid
at
TJ
=
–40°C
to
150°C,
VBB
=
7
to
50
V,
VDD
=
3
to
5.5
V;
unless
otherwise
noted
Characteristics
Symbol
Test Conditions
Min. Typ. Max.
Unit
Logic Inputs and Outputs
FAULT Output (Open drain)
FAULT Output Leakage Current3
RDEAD Current3
Input Low Voltage
Input High Voltage
Input Hysteresis
Input Current (Except RESET)3
Input Pull-down Resistor (RESET)
RESET Pulse Time
VOL
IOH
IDEAD
VIL
VIH
VIHYS
IIN
RPD
tRES
IFAULTOL = 1 mA, fault present
VFAULTO = 5 V, fault not present
RDEAD = GND
0 V < VIN < VDD
–
–1
–200
–
0.7 × VDD
300
–1
–
0.1
–
–
–
–
–
500
–
50
Protection
VREG Undervoltage Lockout
VREGUVON VREG rising
VREGUVOFF VREG falling
7.5 8
6.6 7.1
Bootstrap Undervoltage
VBOOTUV VBOOT falling, VCX – VSX
59 –
Bootstrap Undervoltage Hysteresis
VBOOTUVHYS
– 20
VDD Undervoltage Turn-Off
VDDUV VDD falling
2.45 2.7
VDD Undervoltage Hysteresis
VDDUVHYS
50 100
Overtemperature Flag
TJF Temperature increasing
150 170
Overtemperature Hysteresis
TJFHYS Recovery = TJF – TJFHYS
– 15
1Function is correct, but parameters are not guaranteed below the general limit (7 V).
2See Gate Drive Timing.
3For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
0.4
1
–70
0.3 × VDD
–
–
1
–
3.5
V
μA
μA
V
V
mV
μA
kΩ
μs
8.5
7.6
69
–
2.85
150
–
–
V
V
%VREG
%VREG
V
mV
ºC
ºC
xHI
xLO
GHx
GLx
Gate Drive Timing Diagrams
tp(off)
tDEAD
tDEAD
tp(off)
Complementary
xHI
xLO
GHx
tp(on)
GLx
tp(off)
High side only
xHI
xLO
GHx
GLx
tp(on)
tp(off)
Low side only
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
5 Page 
A4940
Automotive Full Bridge MOSFET Driver
Supply Decoupling
Because this is a switching circuit, there are current spikes from
wwawll.dsuatpapslhieeest4aut .tchoemswitching points. As with all such circuits, the
power supply connections should be decoupled with a ceramic
capacitor, typically 100 nF, between the supply pin and ground.
These capacitors should be connected as close as possible to the
device supply pins, VDD and VBB, and the ground pin, GND.
Power Dissipation
In applications where a high ambient temperature is expected the
on-chip power dissipation may become a critical factor. Careful
attention should be paid to ensure the operating conditions allow
the A4940 to remain in a safe range of junction temperature.
The power consumed by the A4940, PD, can be estimated by :
given
PD = PBIAS +PCPUMP + PSWITCHING
PBIAS = VBB × IBB
PCPUMP = [(2 × VBB) – VREG) × Iav for VBB < 15 V
PCPUMP = (VBB – VREG) × Iav
for VBB > 15 V
Iav = QGATE × VREG × N × fPWM
PSWITCHING = QGATE × VREG × N × fPWM × Ratio
Ratio = 10 / (RGATE + 10)
where N is the quantity of MOSFETs switching during a PWM
cycle. N = 1 for slow decay with diode recirculation, N = 2 for slow
decay with synchronous rectification or fast decay with diode recir-
culation, and N = 4 for fast decay with synchronous rectification.
Layout Recommendations
Careful consideration must be given to PCB layout when designing
high frequency, fast switching, high current circuits. The following
are recommendations regarding some of these considerations:
• The A4940 ground, GND, and the high-current return of the ex-
ternal MOSFETs should return separately to the negative side of
the motor supply filtering capacitor. This minimizes the effect
of switching noise on the device logic and analog reference.
• The exposed thermal pad should be connected to the GND pin
and may form part of the Controller Supply ground (see figure 2).
• Minimize stray inductance by using short, wide copper traces at
the drain and source terminals of all power MOSFETs. This in-
cludes motor lead connections, the input power bus, and the com-
mon source of the low-side power MOSFETs. This will minimize
voltages induced by fast switching of large load currents.
• Consider the use of small (100 nF) ceramic decoupling capaci-
tors across the sources and drains of the power MOSFETs to
limit fast transient voltage spikes caused by the inductance of
the circuit trace.
• The ground connection to RDEAD should be connected inde-
pendently directly to the AGND pin. This sensitive component
should never be connected directly to the supply common or to
a common ground plane. It must be referenced directly to the
AGND pin.
• Supply decoupling for VBB, VREG, and VDD should be con-
nected to the Controller Supply ground which is independently
connected close to the GND pin. The decoupling capacitors should
also be connected as close as possible to the relevant supply pin.
Note that the above are only recommendations. Each application
is different and may encounter different sensitivities. A driver
running a few amps will be less susceptible than one running with
150 A and each design should be tested at the maximum current
to ensure any parasitic effects are eliminated.
RDEAD
VBB
GHB
VREG
GHA
A4940
VDD SA
SB
GLA
RDEAD GLB
AGND GND
Controller Supply Ground
Figure 2. Supply routing suggestions
Optional reverse battery protection
+ Supply
Motor
Power Ground
Supply
Common
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet A4940.PDF ] | |
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