PDF ADC10DV200 Data sheet ( Hoja de datos )

Número de pieza	ADC10DV200
Descripción	200 MSPS Low-Power A/D Converter
Fabricantes	National Semiconductor Corporation
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No Preview Available ! ADC10DV200 February 5, 2009 Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs www.daGtasehneeet4ru.acolmDescription The ADC10DV200 is a monolithic analog-to-digital converter capable of converting two analog input signals into 10-bit dig- ital words at rates up to 200 Mega Samples Per Second (MSPS). The digital output mode is selectable and can be ei- ther differential LVDS or CMOS signals. This converter uses a differential, pipelined architecture with digital error correc- tion and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dy- namic performance. A unique sample-and-hold stage yields a full-power bandwidth of 900MHz. Fabricated in core CMOS process, the ADC10DV200 may be operated from a single 1.8V power supply. The ADC10DV200 achieves approxi- mately 9.6 effective bits at Nyquist and consumes just 280mW at 170MSPS in CMOS mode and 450mW at 200MSPS in LVDS mode. The power consumption can be scaled down further by reducing sampling rates. Applications ■ Communications ■ Medical Imaging ■ Portable Instrumentation ■ Digital Video Features ■ Single 1.8V power supply operation. ■ Power scaling with clock frequency. ■ Internal sample-and-hold. ■ Internal or external reference. ■ Power down mode. ■ Offset binary or 2's complement output data format. ■ LVDS or CMOS output signals. ■ 60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch) ■ Clock Duty Cycle Stabilizer. ■ IF Sampling Bandwidth > 900MHz. Key Specifications ■ Resolution ■ Conversion Rate ■ ENOB ■ SNR ■ SINAD ■ SFDR ■ LVDS Power ■ CMOS Power ■ Operating Temp. Range 10 Bits 200 MSPS 9.6 bits (typ) @Fin=70MHz 59.9 dBFS (typ) @Fin=70MHz 59.9 dBFS (typ) @Fin=70MHz 82 dBFS (typ) @Fin=70MHz 450mW (typ) @Fs=200MSPS 280mW (typ) @Fs=170MSPS −40°C to +85°C. Block Diagram © 2009 National Semiconductor Corporation 300820 30082002 www.national.com 1 page Pin No. Symbol CMOS Output Mode 24-29, 32-35 DA0-DA9 www34.9d7-a-45ta40s, heet4u.comDB0-DB9 37 DRDYA 38 DRDYB 51 ORA 52 ANALOG POWER 8, 16, 18, 59, 60 ORB VA 1, 4, 12, 15, 22, 55, 58, EP DIGITAL POWER AGND 21, 54 VD 31, 45 30, 46 VDR DRGND Equivalent Circuit Description Digital data output pins that make up the 10-bit conversion result for Channel A. DA0 (pin 24) is the LSB, while DA9 (pin 35) is the MSB of the output word. Output levels are CMOS compatible. Digital data output pins that make up the 10-bit conversion result for Channel B. DB0 (pin 39) is the LSB, while DB9 (pin 50) is the MSB of the output word. Output levels are CMOS compatible. Data Ready Strobe for channel A. This signal is used to clock the A-Channel output data. DRDYA is a SDR clock with same frequency as CLK rate and data is valid on the rising edges. Data Ready Strobe for channel B. This signal is used to clock the B-Channel output data. DRDYB is a SDR clock with same frequency as CLK rate and data is valid on the rising edges. Overrange indicator for channel A. A high on this pin indicates that the input exceeded the allowable range for the converter. Overrange indicator for channel B. A high on this pin indicates that the input exceeded the allowable range for the converter. Positive analog supply pins. These pins should be connected to a quiet source and be bypassed to AGND with 0.1 µF capacitors located close to the power pins. The ground return for the analog supply. Exposed pad must be soldered to AGND to ensure rated performance. Positive digital supply pins. These pins should be connected to a quiet source and be bypassed to AGND with 0.1 µF capacitors located close to the power pins. Positive driver supply pin for the output drivers. This pin should be connected to a quiet voltage source and be bypassed to DRGND with a 0.1 µF capacitor located close to the power pin. The ground return for the digital output driver supply. This pin should be connected to the system digital ground. Voltage on DF/DCS Min Max 0 mV 200mV 250 mV 600 mV 750 mV 1250 mV 1400mV VA TABLE 1. Voltage on DF/DCS Pin and Corresponding Chip Response Results DF DCS 1 1 2's complement data, duty cycle correction on 0 0 Offset binary data, duty cycle correction off 1 0 2's complement data, duty cycle correction off 0 1 Offset binary data, duty cycle correction on Suggestions Tie to AGND Leave floating Tie to VA 5 www.national.com 5 Page Timing Diagrams www.datasheet4u.com FIGURE 1. LVDS Output Timing 30082009 FIGURE 2. CMOS Output Timing 11 30082016 www.national.com 11 Page

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