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ADC10D1000 Schematic ( PDF Datasheet ) - National Semiconductor Corporation

Teilenummer ADC10D1000
Beschreibung Dual 1.0 GSPS Or Single 2.0 GSPS A/D Converter
Hersteller National Semiconductor Corporation
Logo National Semiconductor Corporation Logo 




Gesamt 52 Seiten
ADC10D1000 Datasheet, Funktion
PRELIMINARY
November 3, 2008
ADC10D1000
Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D
Converterwww.datasheet4u.com
1.0 General Description
The ADC10D1000 is the latest advance in National's Ultra-
High-Speed ADC family. This low-power, high-performance
CMOS analog-to-digital converter digitizes signals at 10-bit
resolution for dual channels at sampling rates of up to 1.0
GSPS (Non-DES Mode) or for a single channel up to 2.0
GSPS (DES Mode). The ADC10D1000 achieves excellent
accuracy and dynamic performance while dissipating less
than 2.8 Watts. The product is packaged in a leaded or lead-
free 292-ball thermally enhanced BGA package which does
not require a heat sink over the rated industrial temperature
range of -40°C to +85°C.
The ADC10D1000 builds upon the features, architecture and
functionality of the 8-bit GHz family of ADCs. An expanded
feature set includes AutoSync for multi-chip synchronization,
15-bit programmable gain and 12-bit plus sign programmable
offset adjustment for each channel. The improved internal
track-and-hold amplifier and the extended self-calibration
scheme enable a very flat response of all dynamic parameters
beyond Nyquist, producing 9.0 Effective Number of Bits
(ENOB) with a 498 MHz input signal and a 1.0 GHz sample
rate while providing a 10-18 Code Error Rate (CER) Dissipat-
ing a typical 2.8 Watts in Non-Demultiplex Mode at 1.0 GSPS
from a single 1.9 Volt supply, this device is guaranteed to have
no missing codes over the full operating temperature range.
Each channel has its own independent DDR Data Clock,
DCLKI and DCLKQ, which are in phase when both channels
are powered up, so that only one Data Clock could be used
to capture all data, which is sent out at the same rate as the
input sample clock. If the 1:2 Demux Mode is selected, a sec-
ond 10-bit LVDS bus becomes active for each channel, such
that the output data rate is sent out two times slower to relax
data-capture timing requirements. The part can also be used
as a single 2.0 GSPS ADC to sample one of the I or Q inputs.
The output formatting can be programmed to be offset binary
or two's complement and the Low Voltage Differential Signal-
ing (LVDS) digital outputs are compatible with IEEE
1596.3-1996, with the exception of an adjustable common
mode voltage between 0.8V and 1.2V to allow for power re-
duction for well-controlled back planes.
2.0 Features
Excellent accuracy and dynamic performance
Low power consumption
Internally terminated, buffered, differential analog inputs
R/W SPI Interface for Extended Control Mode
Dual-Edge Sampling Mode, in which the I- and Q-channels
sample one input at twice the sampling clock rate
Test patterns at output for system debug
Programmable 15-bit gain and 12-bit plus sign offset
1:1 non-demuxed or 1:2 demuxed LVDS outputs
AutoSync feature for multi-chip systems
Single 1.9V ± 0.1V power supply
292-ball BGA package (27mm x 27mm x 2.4mm with
1.27mm ball-pitch); no heat sink required
LC sampling clock filter for jitter reduction
3.0 Key Specifications
(Non-Demux Non-DES Mode, Fs=1.0 GSPS, Fin = 248 MHz)
Resolution
10 Bits
Conversion Rate
Dual channels at 1.0 GSPS (typ)
Single channel at 2.0 GSPS (typ)
Code Error Rate
ENOB
SNR
SFDR
Full Power Bandwidth
DNL
10-18 (typ)
9.1 bits (typ)
56.7 dBc (typ)
66 dBc (typ)
2.8 GHz (typ)
±0.2 LSB (typ)
Power Consumption
Single Channel Enabled
Dual Channels Enabled
Power Down Mode
1.61W (typ)
2.77W (typ)
59 mW (typ)
4.0 Applications
Wideband Communications
Data Acquisition Systems
Digital Oscilloscopes
5.0 Ordering Information
Industrial Temperature Range (-40°C < TA < +85°C)
ADC10D1000CIUT/NOPB
ADC10D1000CIUT
ADC10D1000RB
NS Package
Lead-free 292-Ball BGA Thermally Enhanced Package
Leaded 292-Ball BGA Thermally Enhanced Package
Reference Board
If Military/Aerospace specified devices are required, please contract the National Semiconductor Sales Office/Dis-
tributors for availability and specifications. IBIS models are available at: http://www.national.com/analog/adc/
ibis_models.
© 2008 National Semiconductor Corporation 300663
www.national.com






ADC10D1000 Datasheet, Funktion
7.0 Connection Diagram
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FIGURE 2. ADC10D1000 Connection Diagram
30066301
The center ground pins are for thermal dissipation and must be soldered to a ground plane to ensure rated performance.
See Section 16.5 Supply and Grounding Recommendations for more information.
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ADC10D1000 pdf, datenblatt
Ball No.
Name
B4
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SDI
Equivalent Circuit
Description
Serial Data-In. In ECM, serial data is shifted into
the device on this pin while SCS signal is
asserted (logic-low).
A3 SDO
D1, D7, E3, F4,
W3, U7
A10, B10, C10,
D10, C17, B18,
B19, B20, U10,
V10, W10, Y10,
V17, W18, W19,
W20
DNC
RSV
Ball No.
A2, A6, B6, C6,
C7, D8, D9, E1,
F1, H4, N4, R1,
T1, U8, U9, W6,
Y2, Y6
G1, G3, G4, H2,
J3, K3, L3, M3,
N2, P1, P3, P4,
R3, R4
A11, A15, C18,
D11, D15, D17,
J17, J20, R17,
R20, T17, U11,
U15, U16, Y11,
Y15
A8, B9, C8, V8,
W9, Y8
J4, K2
Name
VA
VTC
VDR
VE
VbiasI
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Serial Data-Out. In ECM, serial data is shifted out
of the device on this pin while SCS signal is
asserted (logic-low). This output is tri-stated
when SCS is de-asserted.
Do Not Connect. These pins are used for internal
purposes and should not be connected, i.e. left
floating. Do not ground.
Reserved. These pins are used for internal
purposes. They may be left unconnected or
grounded.
TABLE 3. Power and Ground Balls
Equivalent Circuit
Description
Power Supply for the Analog circuitry. This
supply is tied to the ESD ring. Therefore, it must
be powered up before or with any other supply.
Power Supply for the Track-and-Hold and Clock
circuitry.
Power Supply for the Output Drivers.
Power Supply for the Digital Encoder.
Bias Voltage I-channel. This is an externally
decoupled bias voltage for the I-channel. Each
pin should individually be decoupled with a 100
nF capacitor via a low resistance, low inductance
path to GND.
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