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PDF AD9600 Data sheet ( Hoja de datos )
| Número de pieza | AD9600 | |
| Descripción | 1.8 V Dual Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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10-Bit, 105 MSPS/125 MSPS/150 MSPS,
1.8 V Dual Analog-to-Digital Converter
AD9600
www.daFtaEsAhTeeUt4RuE.cSom
SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS
SFDR = 81 dBc to 70 MHz at 150 MSPS
Low power: 825 mW at 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply
Integer 1 to 8 input clock divider
Intermediate frequency (IF) sampling frequencies up to 450 MHz
Internal analog-to-digital converter (ADC) voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input: 1 V p-p to 2 V p-p range
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated receive features
Fast detect/threshold bits
Composite signal monitor
APPLICATIONS
Point-to-point radio receivers (GPSK, QAM)
Diversity radio systems
I/Q demodulation systems
Smart antenna systems
Digital predistortion
General-purpose software radios
Broadband data applications
Data acquisition
Nondestructive testing
PRODUCT HIGHLIGHTS
1. Integrated dual, 10-bit, 150 MSPS/125 MSPS/105 MSPS ADC.
2. Fast overrange detect and signal monitor with serial output.
3. Signal monitor block with dedicated serial output mode.
4. Proprietary differential input maintains excellent SNR
performance for input frequencies up to 450 MHz.
5. The AD9600 operates from a single 1.8 V supply and
features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
6. A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or gray coding), enabling the
clock DCS, power-down mode, and voltage reference mode.
7. The AD9600 is pin compatible with the AD9627-11, AD9627,
and AD9640, allowing a simple migration from 10 bits to
11 bits, 12 bits, or 14 bits.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD
FD[0:3]A
SDIO/ SCLK/
DCS DFS CSB DRVDD
AD9600
FD BITS/THRESHOLD
DETECT
SPI
VIN + A
VIN – A
VREF
SENSE
CML
VIN – B
VIN + B
SHA
ADC
PROGRAMMING DATA
–+
REFERENCE
SELECT
SIGNAL
MONITOR
DIVIDE 1
TO 8
DUTY CYCLE
DCO
STABLIZER GENERATION
SHA
ADC
SERIAL MONITOR
DATA
MULTICHIP FD BITS/THRESHOLD SERIAL MONITOR
SYNC
DETECT
INTERFACE
D9A
D0A
CLK+
CLK–
DCOA
DCOB
D9B
D0B
AGND SYNC
FD[0:3]B
SMI SMI SMI
SDFS SCLK/ SDO/
PDWN OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
Figure 1.
DRGND
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
AD9600
AC SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted.
Table 2.
www.datasheet4u.com
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
WORST OTHER HARMONIC OR SPUR
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
TWO-TONE SFDR
fIN = 29.1 MHz, 32.1 MHz (−7 dBFS )
fIN = 169.1 MHz, 172.1 MHz (−7 dBFS )
CROSSTALK2
ANALOG INPUT BANDWIDTH
AD9600BCPZ-105 AD9600BCPZ-125 AD9600BCPZ-150
Temp Min Typ Max Min Typ Max Min Typ Max Unit
25°C 60.7
25°C 60.6
Full 60.3
25°C 60.6
25°C 60.5
60.6
60.6
60.3
60.6
60.5
60.6
60.6
60.3
60.5
60.4
dB
dB
dB
dB
dB
25°C 60.6
25°C 60.5
Full 60.2
25°C 60.5
25°C 60.4
60.5
60.5
60.2
60.5
60.4
60.5
60.5
60.1
60.4
60.3
dB
dB
dB
dB
dB
25°C 9.9 9.9 9.9 Bits
25°C 9.9 9.9 9.9 Bits
25°C 9.9 9.9 9.9 Bits
25°C 9.9 9.9 9.9 Bits
25°C −87.0
−86.5
−88.5
dBc
25°C −85.0
−85.0
−84.0
dBc
Full
−72.0
−72.0
−72.0 dBc
25°C −84.0
−84.0
−83.5
dBc
25°C −83.0
−83.0
−77 dBc
25°C 85.5
25°C 85.0
Full 72.0
25°C 83.0
25°C 81.0
85.5
85.0
72.0
84.0
81.0
85.5
84.0
72.0
83.5
77
dBc
dBc
dBc
dBc
dBc
25°C −92 −92 −92 dBc
25°C −88
-88
−88 dBc
Full −81 −81 −80 dBc
25°C −86 −86 −86 dBc
25°C −86 −86 −86 dBc
25°C 84 84 84 dBc
25°C 82 82 82 dBc
Full 95 95 95 dB
25°C 650 650 650 MHz
1 See AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel.
Rev. 0 | Page 5 of 72
5 Page 
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
ELECTRICAL
www.dataAshVeDeDt4, uD.VcoDmD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
VIN + A/VIN + B, VIN − A/VIN − B to
AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
CML to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to DRGND
SDIO/DCS to DRGND
SMI SDO/OEB
SMI SCLK/PDWN
SMI SDFS
Output Data Pins to DRGND1
Fast Detect Output Pins to DRGND2
Data Clock Output Pins to DRGND3
ENVIRONMENTAL
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−3.9 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +150°C
1 The output data pins are D0A/D0B to D9A/D9B for the CMOS configuration
and D0+/D0− to D9+/D9− for the LVDS configuration.
2 The fast detect output pins are FD0A/FD0B to FD3A/FD3B for the CMOS
configuration and FD0+/FD0− to FD3+/FD3−.
3 The data clock output pins are DCOA and DCOB for the CMOS configuration
and DCO+ and DCO− for the LVDS configuration.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD9600
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.
Table 7. Thermal Resistance
Package Type
Airflow
Velocity
(m/s)
64 Lead, 9 mm × 9 mm 0
LFCSP (CP-64-3)
1.0
2.0
θJA1, 2
18.8
16.5
15.8
θJC1, 3
0.6
θJB1, 4
6.0
Unit
°C/W
°C/W
°C/W
1 Per JEDEC 51-7 standard and JEDEC 25-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-Std 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, metal (such as metal traces through holes, ground,
and power planes) that is in direct contact with the package
leads reduces the θJA.
ESD CAUTION
Rev. 0 | Page 11 of 72
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9600.PDF ] | |
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