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CDK8307 Schematic ( PDF Datasheet ) - Cadeka

Teilenummer CDK8307
Beschreibung Ultra Low Power ADC
Hersteller Cadeka
Logo Cadeka Logo 




Gesamt 29 Seiten
CDK8307 Datasheet, Funktion
PRELIMINARY Data Sheet
Amplify the Human Experience
CDK8307
12/13-bit, 20/40/50/65MSPS, Eight Channel,
Ultra Lowwww.datasheet4u.com Power ADC with LVDS
FEATURES
n 20/40/50/65MSPS maximum sampling rate
n Low Power Dissipation
– 22mW/channel at 20MSPS
– 34mW/channel at 40MSPS
– 40mW/channel at 50MSPS
– 50mW/channel at 65MSPS
n 72.2dB SNR at 8MHz FIN
n 0.5μs startup time from Sleep
n 15μs startup time from Power Down
n Internal reference circuitry requires no
external components
n Internal offset correction
n Reduced power dissipation modes available
– 32mW/channel at 50MSPS
– 71.5dB SNR at 8MHz FIN
n Coarse and fine gain control
n 1.8V supply voltage
n Serial LVDS output
– 12- and 14-bit output available
n Package alternatives
– TQFP-80
– QFN-64
APPLICATIONS
n Medical Imaging
n Wireless Infrastructure
n Test and Measurement
n Instrumentation
General Description
The CDK8307 is a high performance low power octal analog-to-digital
converter (ADC). The ADC employs internal reference circuitry, a serial control
interface and serial LVDS output data, and is based on a proprietary structure.
An integrated PLL multiplies the input sampling clock by a factor of 12 or 14,
according to the LVDS output setting. The multiplied clock is used for data
serialization and data output. Data and frame synchronization output clocks are
supplied for data capture at the receiver.
Various modes and configuration settings can be applied to the ADC through
the serial control interface (SPI). Each channel can be powered down inde-
pendently and data format can be selected through this interface. A full chip
idle mode can be set by a single external pin. Register settings determines the
exact function of this external pin.
The CDK8307 is designed to easily interface with field-programmable gate
arrays (FPGAs) from several vendors.
The very low startup times of the CDK8307 allow significant power reduction
in duty-cycled systems, by utilizing the Sleep Mode or Power Down Mode when
the receive path is idle.
Block Diagram
Serial Control
Interface
IP1
IN1
ADC
IP2
IN2
ADC
•••
IP8
IN8
ADC
Clock
Input
PLL
LVDS
Digital
Gain
LVDS
Digital
Gain
•••
Digital
Gain
LVDS
•••
LVDS
FCLKP
FCLKN
LCLKP
LCLKN
D1N
D1P
D2N
D2P
D8N
D8P
©2009 CADEKA Microcircuits LLC
www.cadeka.com






CDK8307 Datasheet, Funktion
PRELIMINARY Data Sheet
Pin Assignments (Continued)
Pin No.
Pin Name
51, 54, 55, 56
NC
53 VCM
www.datasheet4u.com58
59
CLKP
CLKN
60 OVDD
61 CSN
62 SDATA
63 SCLK
64 RESETN
QFN-64 (B2 version: AD9222 pinout option)
1, 4, 7, 8, 11, 12, 37, 42, 45, 48,
51, 59, 62
0
AVDD
AVSS
60 IP1
61 IN1
64 IP2
63 IN2
2 IP3
3 IN3
6 IP4
5 IN4
43 IP5
44 IN5
47 IP6
46 IN6
49 IP7
50 IN7
53 IP8
52 IN8
13, 36
DVSS
14, 35
DVDD
41 PD
22 D1P
21 D1N
20 D2P
19 D2N
18 D3P
17 D3N
16 D4P
15 D4N
34 D5P
33 D5N
Description
Not connected
Common mode output pin, 0.5 AVDD
Positive differential input clock
Negative differential input clock.
Digital CMOS inputs supply voltage (1.7V to 3.6V)
Chip select enable. Active low.
Serial data input
Serial clock input
Reset SPI interface
Analog power supply, 1.8V
Analog ground (Exposed paddle, Pin 0, bottom of package)
Positive differential input signal, channel 1
Negative differential input signal, channel 1
Positive differential input signal, channel 2
Negative differential input signal, channel 2
Positive differential input signal, channel 3
Negative differential input signal, channel 3
Positive differential input signal, channel 4
Negative differential input signal, channel 4
Positive differential input signal, channel 5
Negative differential input signal, channel 5
Positive differential input signal, channel 6
Negative differential input signal, channel 6
Positive differential input signal, channel 7
Negative differential input signal, channel 7
Positive differential input signal, channel 8
Negative differential input signal, channel 8
Digital ground
Digital and I/O power supply, 1.8V
Power-down input
LVDS channel 1, positive output
LVDS channel 1, negative output
LVDS channel 2, positive output
LVDS channel 2, negative output
LVDS channel 3, positive output
LVDS channel 3, negative output
LVDS channel 4, positive output
LVDS channel 4, negative output
LVDS channel 5, positive output
LVDS channel 5, negative output
©2009 CADEKA Microcircuits LLC
www.cadeka.com 6

6 Page









CDK8307 pdf, datenblatt
PRELIMINARY Data Sheet
Electrical Characteristics - CDK8307C Continued
Symbol Parameter
Sleep Channel Mode Dissipation
Sleep Channel Mode Savings
Clock Inputs
Maximum Conversion Rate
www.datasheet4u.Mcoinmimum Conversion Rate
Conditions
Power dissipation with all chs in sleep mode
Power dissipation savings per channel off
Min
50
Typ
80
28
Max
Units
mW
mW
MSPS
20 MSPS
Electrical Characteristics - CDK8307D
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted)
Symbol Parameter
Performance
SNR
SINAD
SFDR
HD2
HD3
ENOB
Signal to Noise Ratio
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
Effective number of Bits
Crosstalk
Power Supply
Clock Inputs
Analog supply current
Digital supply current
Analog power Dissipation
Digital power Dissipation
Total power Dissipation
Power Down Dissipation
Sleep Mode Dissipation
Sleep Channel Mode Dissipation
Sleep Channel Mode Savings
Maximum Conversion Rate
Minimum Conversion Rate
Conditions
Min Typ Max Units
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
FIN = 8MHz
Signal applied to 7 chs (FIN0). Measurement
taken on one ch, full scale at FIN1. FIN1 =
8MHz, FIN0 = 9.9MHz
72.2 dBFS
71.5 dBFS
82 dBc
95 dBc
82 dBc
11.6 bits
95 dBc
145 mA
Digital and output driver supply
67 mA
261 mW
121 mW
382 mW
10 µW
96 mW
Power dissipation with all chs in sleep mode 98 mW
Power dissipation savings per channel off
38 mW
65 MSPS
20 MSPS
©2009 CADEKA Microcircuits LLC
www.cadeka.com 12

12 Page





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