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CDK3401 Schematic ( PDF Datasheet ) - Cadeka

Teilenummer CDK3401
Beschreibung (CDK3400 / CDK3401) Triple Video DACs
Hersteller Cadeka
Logo Cadeka Logo 




Gesamt 11 Seiten
CDK3401 Datasheet, Funktion
Data Sheet
Amplify the Human Experience
CDK3400/CDK3401
10-bit, 100/150MSPS, Triple Video DACs
www.datasheet4u.com
features
n 10-bit resolution
n 150 megapixels per second
n ±0.1% linearity error
n Sync and blank controls
n 1.0Vpp video into 37.5Ω or 75Ω load
n Internal bandgap voltage reference
n Double-buffered data for low distortion
n TTL-compatible inputs
n Low glitch energy
n Single +5V power supply
Applications
n Video signal conversion
– RGB
– YCBCR
– Composite, Y, C
n Multimedia systems
General Description
CDK3400/3401 products are low-cost triple D/A converters that are tailored
to fit graphics and video applications where speed is critical. Two speed
grades are available: CDK3400 at 100MSPS and CDK3401 at 150MSPS.
TTL-level inputs are converted to analog current outputs that can drive
25-37.5Ω loads corresponding to doubly-terminated 50-75Ω loads. A sync
current following SYNC input timing is added to the IOG output. BLANK
will override RGB inputs, setting IOG, IOB and IOR currents to zero when
BLANK = L. Although appropriate for many applications, the internal 1.235V
reference voltage can be overridden by the VREF input.
Few external components are required, just the current reference resistor,
current output load resistors, and decoupling capacitors.
Package is a 48-lead TQFP. Fabrication technology is CMOS. Performance is
guaranteed from 0 to 70°C.
Block Diagram
n Image processing
n True-color graphics systems
(1 billion colors)
SYNC
BLANK
SYNC
n Broadcast television equipment
n High-Definition Television (HDTV)
equipment
G9-0 10
10-bit D/A
Converter
IOG
n Direct digital synthesis
B9-0 10
10-bit D/A
Converter
IOB
R9-0 10
CLOCK
+1.235V
Ref
10-bit D/A
Converter
IOR
COMP
R REF
V REF
Ordering Information
Part Number
CDK3400CTQ48
CDK3400CTQ48Y
CDK3401CTQ48
CDK3401CTQ48Y
Package
TQFP-48
TQFP-48
TQFP-48
TQFP-48
Pb-Free
Yes
Yes
Yes
Yes
Moisture sensitivity level for all parts is MSL-3.
RoHS Compliant
Yes
Yes
Yes
Yes
Operating Temp Range
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
Packaging Method
Tray
Tray
Tray
Tray
Package Quantity
250
1,250
250
1,250
©2008 CADEKA Microcircuits LLC
www.cadeka.com






CDK3401 Datasheet, Funktion
Data Sheet
Functional Description
Within the CDK3400/3401 are three identical 10-bit D/A
converters, each with a current source output. External
loads are required to convert the current to voltage out-
puts. Data inputs RGB7-0 are overridden by the BLANK
wwinwp.duatt.asShYeNetC4u=.coHmactivates, sync current from IOS for sync-
on-green video signals.
Digital Inputs
All digital inputs are TTL-compatible. Data is registered
on the rising edge of the CLK signal. Following one stage
of pipeline delay, the analog output changes tDO after the
rising edge of CLK.
Clock Input - CLK
The clock input is TTL-compatible and all pixel data is
registered on the rising edge of CLK. It is recommended
that CLK be driven by a dedicated TTL buffer to avoid
reflection induced jitter, overshoot, and undershoot.
Pixel Data Inputs - R9-0, B9-0, G9-0
TTL-compatible Red, Green and Blue Data Inputs are reg-
istered on the rising edge of CLK.
SYNC and BLANK
SYNC and BLANK inputs control the output level (Figure 2
and Table 1, on the previous page) of the D/A converters
during CRT retrace intervals. BLANK forces the D/A outputs
to the blanking level while SYNC = L turns off a current
source that is connected to the green D/A converter. SYNC
= H adds a 40 IRE sync pulse to the green output, SYNC =
L sets the green output to 0.0V during the sync tip. SYNC
and BLANK are registered on the rising edge of CLK.
Data: 660mV max.
Pedestal: 54mV
Sync: 286mV
Figure 2. Normal Output Levels
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = HIGH, the D/A inputs are added to a pedestal
which offsets the current output. If BLANK = Low, data
inputs and the pedestal are disabled.
Sync Pulse Input - SYNC
Bringing SYNC LOW, turns off a 40 IRE (7.62mA) current
source which forms a sync pulse on the Green D/A con-
verter output. SYNC is registered on the rising edge of
CLK with the same pipeline latency as BLANK and pixel
data. SYNC does not override any other data and should
be used only during the blanking interval.
Since this is a single-supply D/A and all signals are posi-
tive-going, sync is added to the bottom of the Green D/A
range. So turning SYNC OFF means turning the current
source ON. When a sync pulse is desired, the current
source is turned OFF. If the system does not require sync
pulses from the Green D/A converter, SYNC should con-
nected to GND.
Blanking Input - BLANK
When BLANK is LOW, pixel inputs are ignored and the
D/A converter outputs fall to the blanking level. BLANK
is registered on the rising edge of CLK and has the same
pipeline latency as SYNC.
D/A Outputs
Each D/A output is a current source. To obtain a voltage
output, a resistor must be connected to ground. Output
voltage depends upon this external resistor, the reference
voltage, and the value of the gain-setting resistor con-
nected between RREF and GND.
Normally, a source termination resistor of 75Ω is connect-
ed between the D/A current output pin and GND near the
D/A converter. A 75Ω line may then be connected with an-
other 75Ω termination resistor at the far end of the cable.
This “double termination” presents the D/A converter with
a net resistive load of 37.5Ω.
The CDK3400/3401 may also be operated with a single
75Ω terminating resistor. To lower the output voltage
swing to the desired range, the nominal value of the
resistor on RREF should be doubled.
R, G, and B Current Outputs - IOR, IOG, IOB
The R, G, and B current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M
compatible levels into doubly-terminated 75Ω lines. Sync
pulses may be added to the Green D/A output.
©2008 CADEKA Microcircuits LLC
www.cadeka.com 6

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