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CDK2307 Schematic ( PDF Datasheet ) - Cadeka

Teilenummer CDK2307
Beschreibung 12/13-bit Analog-to-Digital Converters
Hersteller Cadeka
Logo Cadeka Logo 




Gesamt 16 Seiten
CDK2307 Datasheet, Funktion
Data Sheet
CDK2307
Dual, 20/40/65/80MSPS, 12/13-bit
wwAw.ndaataslhoeegt4u-.ctoom -Digital Converters
Amplify the Human Experience
FEATURES
n 13-bit resolution
n 20/40/65/80MSPS maximum sampling rate
n Ultra-low power dissipation: 30/55/85/102mW
n SNR 72dB at 80MSPS and 8MHz FIN
n Internal reference circuitry
n 1.8V core supply voltage
n 1.7V – 3.6V I/O supply voltage
n Parallel CMOS output
n 64-pin QFN package
(TQFP-64 package option also available)
n Dual channel
n Pin compatible with CDK2308
APPLICATIONS
n Handheld Communication, PMR, SDR
n Medical Imaging
n Portable Test Equipment
n Digital Oscilloscopes
n Baseband / IF Communication
n Video Digitizing
n CCD Digitizing
General Description
The CDK2307 is a high performance, low power dual Analog-to-Digital Con-
verter (ADC). The ADC employs internal reference circuitry, a CMOS control
interface and CMOS output data, and is based on a proprietary structure.
Digital error correction is employed to ensure no missing codes in the com-
plete full scale range.
Several idle modes with fast startup times exist. Each channel can be inde-
pendently powered down and the entire chip can either be put in Standby
Mode or Power Down mode. The different modes are optimized to allow the
user to select the mode resulting in the smallest possible energy consumption
during idle mode and startup.
The CDK2307 has a highly linear THA optimized for frequencies up to 70MHz.
The differential clock interface is optimized for low jitter clock sources and
supports LVDS, LVPECL, sine wave and CMOS clock inputs.
Functional Block Diagram
CLK_EXT
Ordering Information (QFN-6 Package)
Part Number
Speed Package
CDK2307AILP64
CDK2307AILP64X
20MSPS QFN-64
20MSPS QFN-64
CDK2307BILP64
CDK2307BILP64X
40MSPS QFN-64
40MSPS QFN-64
CDK2307CILP64
CDK2307CILP64X
CDK2307DILP64
CDK2307DILP64X
65MSPS
65MSPS
80MSPS
80MSPS
QFN-64
QFN-64
QFN-64
QFN-64
Moisture sensitivity level for all parts is MSL-2A.
Pb-Free
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RoHS Compliant
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Operating Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Packaging Method
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
©2009 CADEKA Microcircuits LLC
www.cadeka.com






CDK2307 Datasheet, Funktion
Data Sheet
Electrical Characteristics - CDK2307A
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol Parameter
Performance
www.datasheet4u.com
SNR Signal to Noise Ratio
SINAD
Signal to Noise and Distortion Ratio
SFDR
Spurious Free Dynamic Range
HD2 Second order Harmonic Distortion
HD3 Third order Harmonic Distortion
ENOB
Effective number of Bits
XTALK
Crosstalk
Power Supply
AIDD
DIDD
Analog Supply Current
Digital Supply Current
OIDD
Output Driver Supply
Analog Power Dissipation
Digital Power Dissipation
Clock Inputs
Total Power Dissipation
Power Down Dissipation
Sleep Mode 1
Sleep Mode 2
Max. Conversion Rate
Min. Conversion Rate
Conditions
Min Typ
FIN = 2MHz
FIN = 8MHz
FIN FS/2
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN FS/2
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN FS/2
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN FS/2
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN FS/2
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN FS/2
FIN = 20MHz
Signal crosstalk between channels, FIN1 =
8MHz, FIN0 = 9.9MHz
71.5
71
75
-85
-75
11.5
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
20
72.5
72.2
72.1
71.6
72.4
72
71.7
71.3
87
85
80
80
-90
-95
-95
-95
-87
-85
-80
-80
11.7
11.7
11.6
11.6
-105
11.6
1.8
2.9
2.4
20.9
9.2
30.1
9.9
20.5
9.2
15
Max Units
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
bits
bits
bits
bits
dB
mA
mA
mA
mA
mW
mW
mW
µW
mW
mW
MSPS
MSPS
©2009 CADEKA Microcircuits LLC
www.cadeka.com 6

6 Page









CDK2307 pdf, datenblatt
Data Sheet
and that the bandwidth of the transformer is appropriate.
The bandwidth should exceed the sampling rate of the
ADC with at least a factor of 10. It is also important to
keep phase mismatch between the differential ADC inputs
small for good HD2 performance. This type of transformer
wwcwo.udpatlaesdheinetp4uu.tcoismthe preferred configuration for high fre-
quency signals as most differential amplifiers do not have
adequate performance at high frequencies. Magnetic
coupling between the transformers and PCB traces may
impact channel crosstalk, and must hence be taken into
account during PCB layout.
If the input signal is traveling a long physical distance
from the signal source to the transformer (for example a
long cable), kick-backs from the ADC will also travel along
this distance. If these kick-backs are not terminated prop-
erly at the source side, they are reflected and will add to
the input signal at the ADC input. This could reduce the
ADC performance. To avoid this effect, the source must
effectively terminate the ADC kick-backs, or the traveling
distance should be very short. If this problem could not be
avoided, the circuit in Figure 6 can be used.
Note that startup time from Sleep Mode and Power Down
Mode will be affected by this filter as the time required
to charge the series capacitors is dependent on the filter
cut-off frequency.
If the input signal has a long traveling distance, and the
kick-backs from the ADC not are effectively terminated
at the signal source, the input network of Figure 6 can
be used. The configuration is designed to attenuate the
kickback from the ADC and to provide an input impedance
that looks as resistive as possible for frequencies below
Nyquist. Values of the series inductor will however depend
on board design and conversion rate. In some instances
a shunt capacitor in parallel with the termination resistor
(e.g. 33pF) may improve ADC performance further. This
capacitor attenuate the ADC kick-back even more, and
minimize the energy traveling towards the source. How-
ever, the impedance match seen into the transformer will
become worse.
33Ω
47RΩT
33Ω
1:1
optional
120nH 33Ω
6R8TΩ 220Ω
120nH
33Ω
pF
Figure 4. Transformer-Coupled Input
Figure 5 shows AC-coupling using capacitors. Resistors
from the CM_EXT output, RCM, should be used to bias the
differential input signals to the correct voltage. The series
capacitor, CI, form the high-pass pole with these resistors,
and the values must therefore be determined based on
the requirement to the high-pass cut-off frequency.
Ω
pF
Ω
Figure 5. AC-Coupled Input
Figure 6. Alternative Input Network
Clock Input And Jitter Considerations
Typically high-speed ADCs use both clock edges to generate
internal timing signals. In the CDK2307 only the rising
edge of the clock is used. Hence, input clock duty cycles
between 20% and 80% are acceptable.
The input clock can be supplied in a variety of formats.
The clock pins are AC-coupled internally, and hence a
wide common mode voltage range is accepted. Differ-
ential clock sources such as LVDS, LVPECL or differential
sine wave can be connected directly to the input pins.
For CMOS inputs, the CLKN pin should be connected to
ground, and the CMOS clock signal should be connected
to CLKP. For differential sine wave clock input the ampli-
tude must be at least ±800mVpp.
©2009 CADEKA Microcircuits LLC
www.cadeka.com 12

12 Page





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