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CDK1308 Schematic ( PDF Datasheet ) - Cadeka

Teilenummer CDK1308
Beschreibung 10-bit Analog-to-Digital Converters
Hersteller Cadeka
Logo Cadeka Logo 




Gesamt 14 Seiten
CDK1308 Datasheet, Funktion
ADVANCE Data Sheet
CDK1308
Ultra Low Power, 20/40/65/80MSPS,
ww1w0.da-tabshietet4Au.cnomalog-to-Digital Converters (ADCs)
Amplify the Human Experience
FEATURES
n 10-bit resolution
n 20/40/65/80MSPS max sampling rate
n Ultra-Low Power Dissipation:
15/25/38/46mW
n 61.6dB SNR at 8MHz FIN
n Internal reference circuitry
n 1.8V core supply voltage
n 1.7 – 3.6V I/O supply voltage
n Parallel CMOS output
n 40-pin QFN package
n Pin compatible with CDK1307
APPLICATIONS
n Medical Imaging
n Portable Test Equipment
n Digital Oscilloscopes
n IF Communication
General Description
The CDK1308 is a high performance ultra low power analog-to-digital
converter (ADC). The ADC employs internal reference circuitry, a CMOS
control interface and CMOS output data, and is based on a proprietary
structure. Digital error correction is employed to ensure no missing codes in
the complete full scale range.
Two idle modes with fast startup times exist. The entire chip can either be
put in Standby Mode or Power Down mode. The two modes are optimized to
allow the user to select the mode resulting in the smallest possible energy
consumption during idle mode and startup.
The CDK1308 has a highly linear THA optimized for frequencies up to Nyquist.
The differential clock interface is optimized for low jitter clock sources and
supports LVDS, LVPECL, sine wave, and CMOS clock inputs.
Functional Block Diagram
10
Ordering Information
Part Number
CDK1308AILP40
CDK1308BILP40
CDK1308CILP40
CDK1308DILP40
Speed
20MSPS
20MSPS
65MSPS
80MSPS
Package
QFN-40
QFN-40
QFN-40
QFN-40
Moisture sensitivity level for all parts is MSL-3.
Pb-Free
Yes
Yes
Yes
Yes
RoHS Compliant
Yes
Yes
Yes
Yes
Operating Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Packaging Method
Tray
Tray
Tray
Tray
©2008 CADEKA Microcircuits LLC
www.cadeka.com






CDK1308 Datasheet, Funktion
ADVANCE Data Sheet
Electrical Characteristics - CDK1308A
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, unless otherwise noted)
Symbol Parameter
Performance
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SNR Signal to Noise Ratio
SINAD
Signal to Noise and Distortion Ratio
SFDR
Spurious Free Dynamic Range
HD2 Second order Harmonic Distortion
HD3 Third order Harmonic Distortion
ENOB
Effective number of Bits
Power Supply
AIDD
DIDD
Analog Supply Current
Digital Supply Current
OIDD
Output Driver Supply
Analog Power Dissipation
Digital Power Dissipation
Clock Inputs
Total Power Dissipation
Power Down Dissipation
Sleep Mode
Max. Conversion Rate
Min. Conversion Rate
Conditions
FIN = 2MHz
FIN = 8MHz
FIN FS/2
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN FS/2
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN FS/2
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN FS/2
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN FS/2
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN FS/2
FIN = 20MHz
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT enabled
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
Power Dissipation, Sleep mode
Min Typ
61.7
61.6
61.6
61.6
61.7
61.6
60.5
61.6
84.1
85.5
70.3
87.5
-88.8
-89.5
-95.9
-91.4
-89.5
-90.5
-70.3
-89.7
10.0
9.9
9.8
9.9
5.6
1.0
1.7
1.2
10.1
4.8
14.9
9.9
7.7
20
Max Units
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
bits
bits
bits
bits
mA
mA
mA
mA
mW
mW
mW
µW
mW
MSPS
15 MSPS
©2008 CADEKA Microcircuits LLC
www.cadeka.com 6

6 Page









CDK1308 pdf, datenblatt
ADVANCE Data Sheet
a recommended configuration using a transformer. Make
sure that a transformer with sufficient linearity is selected,
and that the bandwidth of the transformer is appropriate.
The bandwidth should exceed the sampling rate of the
ADC with at least a factor of 10. It is also important to
wwkwe.edpatapshhaeseet4um.ciosmmatch between the differential ADC inputs
small for good HD2 performance. This type of transformer
coupled input is the preferred configuration for high fre-
quency signals as most differential amplifiers do not have
adequate performance at high frequencies. If the input
signal is traveling a long physical distance from the signal
source to the transformer (for example a long cable), kick-
backs from the ADC will also travel along this distance. If
these kick-backs are not terminated properly at the source
side, they are reflected and will add to the input signal at
the ADC input. This could reduce the ADC performance.
To avoid this effect, the source must effectively terminate
the ADC kick-backs, or the traveling distance should be
very short. If this problem could not be avoided, the cir-
cuit in Figure 6 can be used.
Note that startup time from Sleep Mode and Power Down
Mode will be affected by this filter as the time required
to charge the series capacitors is dependent on the filter
cut-off frequency.
If the input signal has a long traveling distance, and the kick-
backs from the ADC not are effectively terminated at the
signal source, the input network of Figure 6 can be used.
The configuration is designed to attenuate the kickback
from the ADC and to provide an input impedance that looks
as resistive as possible for frequencies below Nyquist.
Values of the series inductor will however depend on board
design and conversion rate. In some instances a shunt
capacitor in parallel with the termination resistor (e.g. 33pF)
may improve ADC performance further. This capacitor
attenuate the ADC kick-back even more, and minimize the
kicks traveling towards the source. However, the imped-
ance match seen into the transformer becomes worse.
33Ω
47RΩT
33Ω
1:1
optional
120nH 33Ω
6R8TΩ 220Ω
120nH
33Ω
pF
Figure 4. Transformer-Coupled Input
Figure 5 shows AC-coupling using capacitors. Resistors
from the CM_EXT output, RCM, should be used to bias the
differential input signals to the correct voltage. The series
capacitor, CI, form the high-pass pole with these resistors,
and the values must therefore be determined based on
the requirement to the high-pass cut-off frequency.
Ω
pF
Ω
Figure 5. AC-Coupled Input
Figure 6. Alternative Input Network
Clock Input And Jitter Considerations
Typically high-speed ADCs use both clock edges to gener-
ate internal timing signals. In the CDK1308 only the rising
edge of the clock is used. Hence, input clock duty cycles
between 20% and 80% is acceptable.
The input clock can be supplied in a variety of formats.
The clock pins are AC-coupled internally, and hence a wide
common mode voltage range is accepted. Differential
clock sources as LVDS, LVPECL or differential sine wave
can be connected directly to the input pins. For CMOS
inputs, the CLKN pin should be connected to ground, and
the CMOS clock signal should be connected to CLKP. For
differential sine wave clock input the amplitude must be
at least ±800mVpp.
©2008 CADEKA Microcircuits LLC
www.cadeka.com 12

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