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PDF CDK1305 Data sheet ( Hoja de datos )
| Número de pieza | CDK1305 | |
| Descripción | 40 MSPS 175mW A/D Converter | |
| Fabricantes | Cadeka | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CDK1305 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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Data Sheet
Amplify the Human Experience
CDK1305
10-bit, 40 MSPS 175mW A/D Converter
www.datasheet4u.com
features
n 40 MSPS converter
n 175mW power dissipation
n On-chip track-and-hold
n Single +5V power supply
n TTL/CMOS outputs
n 5pF input capacitance
n Tri-state output buffers
n High ESD protection: 3,500V minimum
n Selectable +3V or +5V logic I/O
Applications
n All high-speed applications where low
power dissipation is required
n Video imaging
n Medical imaging
n Radar receivers
n IR imaging
n Digital communications
General Description
The CDK1305 is a 10-bit, low power analog-to-digital converter capable
of minimum word rates of 40 MSPS. The on-chip track-and-hold function
assures very good dynamic performance without the need for external
components. The input drive requirements are minimized due to the CDK1305
low input capacitance of only 5pF.
Power dissipation is extremely low at only 175mW typical at 40 MSPS with
a power supply of +5.0V. The digital outputs are +3V or +5V, and are user
selectable. The CDK1305 is pin-compatible with an entire family of 10-bit,
CMOS converters (CDK1304/05/06), which simplifies upgrades. The CDK1305
has incorporated proprietary circuit design* and CMOS processing
technologies to achieve its advanced performance. Inputs and outputs are
TTL/CMOS-compatible to interface with TTL/CMOS logic systems. Output
data format is straight binary.
The CDK1305 is available in 28-lead SOIC and 32-lead small (7mm square)
TQFP packages over the commercial temperature range.
Block Diagram
Ordering Information
Part Number
CDK1305CSO28
Package
SOIC-28
Pb-Free
Yes
CDK1305CSO28_Q
CDK1305CTQ32
SOIC-28
TQFP-32
No
Yes
CDK1305CTQ32_Q
TQFP-32
No
Moisture sensitivity level for SOIC-28 is MSL-1 and TQFP is MSL-3.
RoHS Compliant
Yes
No
Yes
No
Operating Temperature Range
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
Packaging Method
Rail
Rail
Rail
Rail
©2008 CADEKA Microcircuits LLC
www.cadeka.com
1 page  
Data Sheet
Electrical Characteristics
(TA = TMin to TMax, AVDD = DVDD = OVDD = +5V, VIN = 0 to 4V, ƒclk = 40 MSPS, VRHS = 4V, VRLS = 0V; unless otherwise noted)
Symbol Parameter
SFDR
Spurious Free Dynamic Range
Differential Phase
www.datasheet4u.Dcoifmferential Gain
Digital Inputs
Logic “1“ Voltage(1)
Logic “0“ Voltage(1)
Maximum Input Current Low(1)
Maximum Input Current High(1)
Input Capacitance
Digital Outputs
Logic “1“ Voltage(1)
Logic “0“ Voltage(1)
TR Rise Time
TF Fall Time
Output Enable to Data Output Delay
Power Supply Requirements
OVDD
DVDD
AVDD
AIDD
DIDD
Digital Voltage Supply(2)
Digital Voltage Current(1)
Power Dissipation(1)
Conditions
ƒIN = 1MHz
IOH = 0.5mA
IOL = 1.6mA
15pF load
15pF load
20pF load, TA = 25°C
50pF load over temp
Min
2.0
-10
-10
3.5
3.0
4.75
4.75
Typ
63
±0.3
±0.3
+5
10
10
10
22
5.0
5.0
17
18
175
Max
Units
pspp
deg
%
V
0.8 V
+10 μA
+10 μA
pF
V
0.4 V
ns
ns
ns
ns
5.0
5.25
5.25
22
23
225
V
V
V
mA
mA
mW
Notes:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
©2008 CADEKA Microcircuits LLC
www.cadeka.com 5
5 Page 
Data Sheet
Input Protection
All I/O pads are protected with an on-chip protection circuit
shown in Figure 6. This circuit provides ESD robustness
to 3.5kV and prevents latch-up under severe discharge
conditions without degrading analog transition times.
www.datasheet4u.com
Digital Outputs
The digital outputs (D0–D10) are driven by a sepa-
rate supply (OVDD) ranging from +3 V to +5 V. This
feature makes it possible to drive the CDK1305 TTL/CMOS
compatible outputs with the user’s logic system supply.
The format of the output data (D0–D9) is straight binary.
(See Table 3.) The outputs are latched on the rising edge
of CLK. These outputs can be switched into a tri-state
mode by bringing EN high.
Table 3. Output Data Information
Analog Input
+F.S. + 1/2 LSB
+F.S. –1/2 LSB
+1/2 F.S.
+1/2 LSB
0.0V
Overrange D10
1
0
0
0
0
Output Code D9-D0
1111111111
1 1 1 1 1 1 1 1 1Ø
ØØ ØØØØ ØØØØ
000000000Ø
0000000000
(Ø indicates the flickering bit between logic 0 and 1.)
Figure 7. On-Chip Protection Circuit
Power Supply Sequencing Considerations
All logic inputs should be held low until power to the
device has settled to the specific tolerances. Avoid power
decoupling networks with large time constants that could
delay VDD power to the device.
Clock Input
The CDK1305 is driven from a single-ended TTL-input
clock. Because the pipelined architecture operates on the
rising edge of the clock input, the device can operate over
a wide range of input clock duty cycles without degrading
the dynamic performance.
Overrange Output
The Overrange Output (D10) is an indication that the
analog input signal has exceeded the positive fullscale
input voltage by 1 LSB. When this condition occurs, D10
will switch to logic 1. All other data outputs (D0 to D9)
will remain at logic 1 as long as D10 remains at logic 1.
This feature makes it possible to include the CDK1305 in
higher resolution systems.
Evaluation Board
The TBD evaluation board is available to aid designers in
demonstrating the full performance of the CDK1305. This
board includes a reference circuit, clock driver circuit, out-
put data latches, and an on-board reconstruction of the
digital data. An application note describing the operation
of this board, as well as information on the testing of the
CDK1305, is also available. Contact the factory for price
and availability.
©2008 CADEKA Microcircuits LLC
www.cadeka.com 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CDK1305.PDF ] | |
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