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PDF DS4100H Data sheet ( Hoja de datos )
| Número de pieza | DS4100H | |
| Descripción | 100MHz HCSL Clock Generator | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Rev 0; 11/07
100MHz HCSL Clock Generator
www.datasheet4u.com
General Description
The DS4100H is a low-jitter 100MHz clock generator
with a high-speed current steering logic (HCSL) output.
It combines an AT-cut crystal, an oscillator, and a low-
noise phase-locked loop (PLL) in a 5mm by 3.2mm
ceramic package. Typical phase jitter is 0.9psRMS from
12kHz to 20MHz. The device operates from a single
+3.3V supply.
PCI Express®
Applications
Features
♦ 100MHz Output Frequency
♦ 3.3V ±5% Operating Voltage
♦ HCSL Output
♦ Phase Jitter (RMS): 0.9ps Typical
♦ ±39ppm Frequency Stability Over Voltage,
Temperature, 10 Years of Aging
♦ Output-Enable (OE) Control Input
♦ 5mm x 3.2mm x 1.49mm Ceramic Package (LCCC)
♦ Pb Free/RoHS Compliant
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE TOP
MARK
DS4100H+ -40°C to +85°C 10 LCCC
10H
+Denotes a lead-free package. The lead finish is JESD97
category e4 (Au over Ni) and is compatible with both lead-based
and lead-free soldering processes.
Typical Operating Circuit
3.3V
VCC
OE OUTP
RS
475Ω
±1%
DS4100H
RREF OUTN
GND
RS
PCI Express
LOAD OR
CONNECTOR
RT RT
Pin Configuration
TOP VIEW
N.C.
+
OE 1
N.C.
6 VCC
RREF 2
DS4100H
5 OUTN
GND 3 *EP
4 OUTP
N.C. N.C.
(5.00mm × 3.20mm × 1.49mm)
*EXPOSED PAD
PCI Express is a registered trademark of PCI-SIG Corp.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
100MHz HCSL Clock Generator
www.datasheet4u.com
OUTP
OUTPUT
BUFFER
OUTN
RS
RS
Z0 OUTP
Z0 = 50Ω, 35in LENGTH
CL
RECEIVER
Z0
RT RT
RT = 50Ω
OUTN
CL
CL = 2pF
RS = 0Ω FOR TEST, 0 TO 33Ω TO MINIMIZE RINGING IN APPLICATION.
CL = SIMULATES RECEIVER INPUT CAPACITANCE FOR TEST ONLY.
Figure 2. Typical Termination for HCSL Driver and Test Conditions
0.7 x VCC
OE
tPZH
OUTP
GND
OUTN
GND
tPZL
Figure 3. HCSL Output Timing Diagram When OE is Enabled and Disabled
0.3 x VCC
tPZ
PIN
1
2
3
4
5
6
7–10
—
NAME
OE
RREF
GND
OUTP
OUTN
VCC
N.C.
EP
Pin Description
FUNCTION
Output Enable. On-chip pullup resistor. If connected to logic-high or left open, the clock output is
enabled. If connected to logic-low, the output is three-stated.
Connect a 475 ±1% resistor from RREF to ground.
Ground
Positive Clock Output. Requires a series resistor and a pulldown resistor.
Negative Clock Output. Requires a series resistor and a pulldown resister.
+3.3V Supply Input. Device power can range from 3.135V to 3.465V.
No Connection
Exposed Paddle. The exposed pad must be used for thermal relief. This pad can be connected to
ground.
_______________________________________________________________________________________ 5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet DS4100H.PDF ] | |
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