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WED3EG7232S-JD3 Schematic ( PDF Datasheet ) - White Electronic Designs

Teilenummer WED3EG7232S-JD3
Beschreibung 256MB - 32Mx72 DDR SDRAM UNBUFFERED
Hersteller White Electronic Designs
Logo White Electronic Designs Logo 




Gesamt 12 Seiten
WED3EG7232S-JD3 Datasheet, Funktion
www.datasheet4u.com
WED3EG7232S-JD3
PRELIMINARY
256MB – 32Mx72 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
DDR200, DDR266, DDR333 amd DDR400
• JEDEC design specications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2, 2.5 (clock)
Programmable Burst Length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply:
• VCC = VCCQ = +2.5V ± 0.2V (100, 133 and
166MHz)
• VCC = VCCQ = +2.6V ± 0.1V (200MHz)
JEDEC 184 pin DIMM package
• JD3 PCB height: 30.48 (1.20") Max
DESCRIPTION
The WED3EG7232S is a 32Mx72 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of nine 32Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualied or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
DDR400 @CL=3
200MHz
3-3-3
OPERATING FREQUENCIES
DDR333 @CL=2.5
DDR266 @CL=2
166MHz
133MHz
2.5-3-3
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
June 2006
Rev. 6
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






WED3EG7232S-JD3 Datasheet, Funktion
www.datasheet4u.com
WED3EG7232S-JD3
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
4. Timing Patterns :
• DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
• DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,
tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR400 (200MHz, CL=3) : tCK=5ns, BL=4,
tRCD=15*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
1.
2.
3.
4.
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
Typical Case : VCC=2.5V, T=25°C
Worst Case : VCC=2.7V, T=10°C
Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
Timing Patterns :
• DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
repeat the same timing with random address
changing; 100% of data changing at every
burst
• DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR333 (166MHz, CL=2.5) : tCK=6ns,
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR400 (200MHz, CL=3) : tCK=5ns,
BL=4, tRRD=10*tCK, tRCD=15*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
June 2006
Rev. 6
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page









WED3EG7232S-JD3 pdf, datenblatt
www.datasheet4u.com
WED3EG7232S-JD3
PRELIMINARY
Document Title
256MB- 32Mx72 DDR SDRAM UNBUFFERED
DRAM DIE OPTIONS:
SAMSUNG: H-Die
MICRON: T26Z: G-Die
Revision History
Rev #
Rev 1
Rev 2
Rev 3
Rev 4
Rev 5
Rev 6
History
Release Date Status
Created Datasheet
Corrected Mechanical Drawing
3.1 Removed "ED" for Part Marking
3.2 Changed from Advanced to Preliminary
3-6-02
5-22-02
5-04
Advanced
Advanced
Preliminary
4.1 Added 333 and 400HMz speed
4.2 Added lead-free and RoHS notes
12-04
Preliminary
5.1 Added "ED" back to part number
5.2 Added JEDEC Standard PBC
5.3 Added "D3" package option "NOT RECOMMENDED FOR
NEW DESIGNS"
5-05
6.1 Remove "D3" package option
6.2 Added "Part Numbering Guide"
6.3 Added DRAM die options
6-06
Preliminary
Preliminary
June 2006
Rev. 6
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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