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PBL3796 Schematic ( PDF Datasheet ) - Ericsson

Teilenummer PBL3796
Beschreibung Subscriber Line Interface Circuit
Hersteller Ericsson
Logo Ericsson Logo 




Gesamt 22 Seiten
PBL3796 Datasheet, Funktion
April 1997
www.DataSheet4U.com
PBL 3796, PBL 3796/2
Subscriber Line
Interface Circuit
Description
Key Features
PBL 3796 is an analog Subscriber Line Interface Circuits (SLICs), which are fabrica-
ted in a 75 V bipolar, monolithic process.
The programmable battery feed is resistive with short-loop current limiting. A
switch-mode regulator reduces on-chip power dissipation in the active state. In the
standby state, power dissipation is further reduced, while still permitting supervisory
functions to be active.
Tip-ring polarity is reversible without altering SLIC supervisory and voice frequency
(vf) functions. Tip and ring outputs can be set to high impedance states. These and
other operating states are activated via a parallel, four bit control word.
An external resistor controls the off-hook detector threshold current. The ring trip
detector can operate with both balanced and unbalanced ringing systems. The two
detectors are read via a shared output.
Ring and test relay drivers with internal clamp diodes are provided.
The complex or real two-wire impedance is set by a scaled, lumped element
network.
Two- to four-wire and four- to two-wire signal conversion is provided by the SLIC in
conjunction with either a conventional or a programmable CODEC/filter.
Longitudinal line voltages are suppressed by a control loop within the SLIC.
Packages are 28-pin, dual-in-line; 32-pin or 44-pin j-leaded chip carrier.
The difference between PBL 3796 and PBL 3796/2 is mainly the longitudinal
balance spec.
4
RINGRLY
5
TESTRLY
26
DR
25
DT
27
TIPX
22
HPT
23
HPR
28
RINGX
2
VREG
L
VBAT
GND2
6
7
1
Ring Relay
Driver
Test Relay
Driver
Ring Trip
Comparator
Two-wire
Interface
Input
Decoder
and
Control
Loop
Detector
VF Signal
Transmission
Line Feed
Controller and
Longitudinal
Suppression
Switching
Regulator
9 8 10
CHS VQBAT CHCLK
3
VCC
20
VEE
16
C1
14
C2
15
C3
11
C4
12
E0
13
DET
24
RD
21
VTX
19
RSN
17
RDC
18
GND1
• On-chip switch mode regulator to
minimize power dissipation
• Programmable, resistive battery feed
with short-loop current limiting
• Line feed characteristics independent
of battery variations
• Tip-ring polarity reversal function
• Tip and ring open circuit state; tip open
with ring active state
• Detectors:
- programmable loop current detector
- ring trip detector
• Ring and test relay drivers
• Line terminating impedance, complex
or real, set by a simple external
network
• Hybrid function with conventional or
programmable CODEC/filters
• 70 dB longitudinal to metallic balance
• 79 mA peak longitudinal current
suppression
• Idle noise < 10 dBrnC, < -80 dBup
PBL 3796
379P6BL
Figure 1. Block diagram. Pin numbers refer to the dual-in-line package.
4-105






PBL3796 Datasheet, Funktion
PBL 3796
Parawmwetwer.DataSheet4U.com
Ref
fig Conditions
Noise
Idle channel noise at two-wire
(TIPX-RINGX) or four-wire (VTX) port
6
ERXC=-mEsL g=
0, Notes 2,
weighting
10,
14
Psophometrical weighting
Single frequency out-of-band noise (Note 11)
Metallic, VTR
Longitudinal, VLo
Longitudinal, V
Lo
7 12 kHz f 1 MHz
7 12 kHz f 90 kHz
7 90 kHz f 1 MHz
Total harmonic distortion
Two-wire to four-wire,
Four-wire to two-wire
6 0.3kHz f 3.4kHz
0 dBu, 1 kHz test signal, Note 2
Intermodulation
Type 2f1 - f2
Two-wire to four-wire
Four-wire to two-wire
Type f1 ± 50 Hz
Two-wire to four-wire
6
0.3 kHz
Level f1
<
=
lfe1,vfe2l
< 3.4 kHz,
f2 = -25 to
0
dBv
f1 nf2, f2 nf1, Note 2
E =0
ERL X= 0
6
0.3kHz <
Level 50
Hf1z<=3l.e4vkeHl zf1
-
14
dB,
Level f = -15 dBv to 0 dBv
1
f1 n • 50 Hz, Note 2
ERX = 0
Battery feed characteristics
Apparent battery voltage, E
BAp
Feed resistance (RFeed)
to programming resistance (RDC1+RDC2)
conversion factor, K1
Active state short circuit loop
current, ILShAct
Active state loop current limiting
threshold, I
LLimAct
Active state line current
Stand-by state short circuit loop
current, ILShSb
Stand-by state loop current limiting
threshold, ILLimSb
Active state
Active, polarity reversal state
Active and
active, polarity reversal state
K1 =
R +R
DC1
DC2
R
Feed
RDC1 +RDC2 = 2.5 k
145
ILShAct = RDC1 + RDC2
RDC1 + RDC2 = 2.5 k
ILLimAct =
115
, Note 12
RDC1 + RDC2
VBat = -43.5V to -58.0V
ZL=2000
RDC1+RDC2=2.5k
RDC1 +RDC2 = 2.5 k
ILShSb =
80
RDC1 + RDC2
R
DC1
+
R
DC2
=
2.5
k
45
I=
LLimSb
RDC1 + RDC2
, Note 12
+
V'Lo + 67.5
C
56.25
VTR
67.5 C
TIPX
27
20
I Ldc
PBL3796,
PBL 3796/2
20
RINGX
28
4-110
Min
Typ
Max
Unit
10 14 dBrnC
-80 -76 dBup
-58 -55 dBV
-68 -63 dBV
-53 -50 dBV
-64 -50 dB
-60 -50 dB
-60 -50 dB
47.5
-52.5
4.75
-65 -50 dB
50 52.5 V
-50 -47.5 V
5.00 5.25 Ratio
53 59 65 mA
46 mA
16 mA
26 32 38 mA
18 mA
Figure 7. Single-frequency out of band
noise.
Resistance values in ,
VLo = 1.6 • V'Lo
1/ωC << 100

6 Page









PBL3796 pdf, datenblatt
PBL 3796
www.DataSheet4U.com
TIP
Line Test
Channel Test
RING
KT
KT
Ringing
(90 Vrms + VBat)
KT
KT
RRT
CRT
R3 Note 1
RF1
KR
Note 5
KR
RF2
VBat
K1 K1
U3
AG
K2 K2
KR
VEE
R4
R2
VBat
CTisp
D5
High
Voltage
R1
DT 38/25
DR 40/26
TIPX 42/27
CTC HPT 34/22
CHP HPR 35/23
RINGX 43/28
CRC
U1 Low
Voltage
-5V
PBL 3796 25/- RSG
37/24 RD
CD
RSG
RD
VEE
31/20
VCC
4/3
VTX
32/31
27/18 GND1
29/19 RSN
RT
+5V
RINGRLY 6/4
KT TESTRLY 7/5
RDC1
26/17 RDC
RDC2
CDC
RTX
RRX
U2
RFB
VT
+
RB VRX
Combination
CODEC/Filter
VBat
RBat
D7
VBAT 10/7
CBat
GND2
2/1
CFlt
VREG
3/2
16/11 C4
22/15 C3
21/14 C2
23/16 C1
U1
U2
U3
RB
RFB
RRX
RT
RTX
RCh
R1, R3
R2
R
4
R
D
RDC1, RDC2
R
SG
R
RT
RBat
RF1, RF2
C
Bat
C
Tisp
CCh1
C
Ch2
C
D
CDC
CFlt
CHP
PBL 3796 Subcriber Line Interface
Circuit (SLIC)
Combination CODEC/Filter
Secondary protection (e.g. Texas
Instrument TISP PBL 1), Note 7.
Resistor 27.4 k1% 1/4 W
Resistor dependent on application
Resistor 42.2 k1% 1/4 W
Resistor 82.5 k1% 1/4 W
Resistor 27.4 k1% 1/4 W
Resistor 909 2% 1/4 W
Resistor 200 k5% 1/4 W
Resistor 909 k5% 1/4 W
Resistor 1.21 M5% 1/4 W
Resistor 51.1 k5% 1/4 W
Resistor 1.24 k5% 1/4 W
Resistor Note 3 5% 1/4 W
Resistor 150 5% 2 W
Resistor Note 4
Resistor 40 1% RF1/RF2 ratio
match (e.g. Ericsson Components
PBR 51- series)
Capacitor0.47 µF 20% 100V
Capacitor 220 nF 20% 100V
Capacitor 47 nF 10% 100V
Capacitor1500 pF 10% 100V
Capacitor6200 pF 20% 10V
Capacitor 1.2 µF 10% 10V
Capacitor0.47 µF 10% 100V
Capacitor0.22 µF 10% 100V
L D1
RCh
D6
L 8/6
VQBAT
11/8
CQ
VEE
CCh1
CHS 12/9
CCh2
20/13 DET
19/- E0
17/12 E1
NC 14/10 CHCLK
Note 2
256 kHz System Control
Clock
Interface
CQ
CRT
CTC, CRC
D1
D6
D7
L
KT
KR
Capacitor 0.33 µF 20% 100V
Capacitor 0.39 µF 20% 100V
Capacitor 2200 pF10% 100V
Diode
100 V100 mA 10 nS (e.g.
1N4448)
Diode
Note 6
Diode
100 V500 mA
Inductor 1 mH 10%r 15
(e.g. Siemens B78108-S1105-J, J. W. Miller
9220-28, Nytronics RFC-S, or Ericsson REG
522 7103)
Relay, test 4C contacts
Relay, ring 2C contacts
Notes
1 The ringtrip network may alternatively be located on
the RING lead side. The ringtrip network may also be
configured for balanced ringing as shown in figure 20.
2 It is recommended to connect pins marked "NC" (44-
pin package pins # 1, 5, 9, 13, 15, 18, 24, 28, 30, 33,
36 & 39) to ground.
3. RSG is open circuit for VBat = -48 V and shorted to VEE
for V = -63 V. For intermediate battery voltages,
Bat
calculate as described in the section, “Battery feed,
Case 2".
4. RBat for one line is recommended to be 5,65% 1/
4W. However the resistor can be shared between
several lines, for instance 1 5% 1W for eight lines.
5. The ground terminals of the secondary protection
should be connected to the common ground on the
Printed Board Assembly with a track as short and
wide as possible, preferrable a ground plane.
6. For diode type, refer to section "Power-Up
Sequence".
7. Texas Instrument TISP PBL2 should be used when
PBL 3796 is programmed for a maximum line current
exceeding 60 mA.
Figure 11. PBL 3796 application example.
4-116

12 Page





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