|
|
PDF EN29F080 Data sheet ( Hoja de datos )
| Número de pieza | EN29F080 | |
| Descripción | 8 Megabit (1024K x 8-bit) Flash Memory | |
| Fabricantes | EON | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de EN29F080 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DatEaSNhee2t49UF.co0m80
8 Megabit (1024K x 8-bit) Flash Memory
EN29F080
FEATURES
• 5.0V ± 10%, single power supply operation
- Minimizes system level power requirements
• Manufactured on 0.35 µm process technology
• High performance
- Access times as fast as 45 ns
• Low power consumption
- 25 mA typical active read current
- 30 mA typical program/erase current
- 1 µA typical standby current (standard access
time to active mode)
• Flexible Sector Architecture:
- 16 uniform sectors of 64Kbytes each
- Supports full chip erase
- Individual sector erase supported
- Group sector protection:
Hardware method of locking of sector groups
to prevent any program or erase operations
within that sector group
Additionally, temporary Sector Group
Unprotect allows code changes in previously
locked sectors
• High performance program/erase speed
- Byte program time: 10µs typical
- Sector erase time: 500ms typical
- Chip erase time: 16s typical
• Low Standby Current
- 1µA CMOS standby current-typical
- 1mA TTL standby current
• Low Power Active Current
- 30mA active read current
- 30mA program/erase current
• JEDEC Standard program and erase
commands
• JEDEC standard DATA polling and toggle
bits feature
• Sector Unprotect Mode
• Embedded Erase and Program Algorithms
• Erase Suspend / Resume modes:
Read and program another Sector during
Erase Suspend Mode
• 0.35 µm double-metal double-poly
triple-well CMOS Flash Technology
• Low Vcc write inhibit < 3.2V
• >100K program/erase endurance cycle
• Ready/Busy# output (RY/BY#)
- Provides a hardware method for detecting
program or erase cycle completion.
• Hardware reset pin (Reset#)
- Resets internal state machine to read mode
GENERAL DESCRIPTION
The EN29F080 is a 8-Megabit, electrically erasable, read/write non-volatile flash memory. Organized
into 1024K words with 8 bits per word, the 8M of memory is arranged in eight uniform sectors of
64Kbytes each. Any byte can be programmed typically in 10µs. The EN29F080 features 5.0V
voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT
states in high-performance microprocessor systems.
The EN29F080 has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable ( W E )
controls, which eliminate bus contention issues. This device is designed to allow either single (or
multiple) Sector or full chip erase operation, where each Sector can be individually protected against
program/erase operations or temporarily unprotected to erase or program. The device can sustain a
minimum of 100K program/erase cycles on each Sector.
4800 Great America Parkway, Suite 202
1
Santa Clara, CA 95054
Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680
Fax: 408-235-8685
1 page  
EN29F080
www.DataSheet4U.com
TABLE 3. OPERATING MODES
8M FLASH USER MODE TABLE
C E WE OE A9 A8 A6 A1 A0 Ax/y
DQ(0-7)
USER MODE
STANDBY
READ
OUTPUT DISABLE
READ
MANUFACTURE ID
READ DEVICE ID
VERIFY SECTOR
PROTECT
ENABLE SECTOR
PROTECT
SECTOR UNPROTECT
WRITE
TEMPORARY SECTOR
UNPROTECT
H
L
L
L
L
L
L
L
L
X
X X XXXXX X
HI-Z
H L A9 A8 A6 A1 A0 Ax/y
DQ(0-7)
H H A9 A8 A6 A1 A0 Ax/y
HI-Z
H L VID L/H L L L X MANUFACTURE
ID
H L VID L/H L L H X DEVICE ID(T/B)
H L VID X L H L X
CODE
L VID VID X L X X
X
X
L VID VID X H H L
X
L H A9 A8 A6 A1 A0 Ax/y
X X XXXXX X
X
DIN(0-7)
X
NOTES:
1) L = VIL, H = VIH, VID = 11.5V ± 0.5V
2) X = Don’t care, either VIH or VIL
TABLE 4. DEVICE IDENTIFICTION
8M FLASH MANUFACTURER/DEVICE ID TABLE
A8 A6 A1 A0
READ CONTINUATION
L
L
LL
MANUFACTURER ID
READ
H L LL
MANUFACTURER ID
READ CONTINUATION
L
L
LH
DEVICE ID
READ DEVICE ID
H L LH
DQ(7-0)
HEX
MANUFACTURER ID
7F
MANUFACTURER ID
1C
DEVICE ID
7F
DEVICE ID
08
4800 Great America Parkway, Suite 202
5
Santa Clara, CA 95054
Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680
Fax: 408-235-8685
5 Page 
EN29F080
Sector Erase Command Sequence
www.DataSheet4U.com
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by
the address of the sector to be erased, and the sector erase command. The Command Definitions table
shows the address and data requirements for the sector erase command sequence.
This device does not support multiple sector erase commands. Sector Erase operation will
commence immediately after the first 30h command is written. The first sector erase operation must
finish before another sector erase command can be given.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or
DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the
algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC
Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing
waveforms.
Erase Suspend / Resume Command
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for erasure. This command is valid only during the
sector erase operation. The Erase Suspend command is ignored if written during the chip erase operation
or Embedded Program algorithm. Addresses are don’t-cares when writing the Erase Suspend command.
When the Erase Suspend command is written during a sector erase operation, the device requires a
maximum of 20 µs to suspend the erase operation.
After the erase operation has been suspended, the system can read array data from or program data to
any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.)
Normal read and write timings and command definitions apply. Reading at any address within erase-
suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status”
for information on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data
within non-suspended sectors. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more
information.
The system must write the Erase Resume command (address bits are don’t-care) to exit the erase
suspend mode and continue the sector erase operation. Further writes of the Resume command are
ignored. Another Erase Suspend command can be written after the device has resumed erasing.
4800 Great America Parkway, Suite 202
11
Santa Clara, CA 95054
Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680
Fax: 408-235-8685
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EN29F080.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| EN29F080 | 8 Megabit (1024K x 8-bit) Flash Memory | EON |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |