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Número de pieza | RJK0329DPB | |
Descripción | Silicon N Channel Power MOS FET Power Switching | |
Fabricantes | Renesas Technology | |
Logotipo | ||
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Silicon N Channel Power MOS FET
Power Switching
Features
• High speed switching
• Capable of 4.5 V gate drive
• Low drive current
• High density mounting
• Low on-resistance
RDS(on) = 1.8 mΩ typ. (at VGS = 10 V)
• Pb-free
Outline
RENESAS Package code: PTZZ0005DA-A
(Package name: LFPAK)
5
1 234
4
G
5
D
SSS
123
REJ03G1638-0400
Rev.4.00
Apr 10, 2008
1, 2, 3
4
5
Source
Gate
Drain
Absolute Maximum Ratings
Item
Drain to source voltage
Gate to source voltage
Drain current
Drain peak current
Body-drain diode reverse drain current
Avalanche current
Avalanche energy
Channel dissipation
Channel to Case Thermal Resistance
Channel temperature
Storage temperature
Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1%
2. Value at Tch = 25°C, Rg ≥ 50 Ω
3. Tc = 25°C
Symbol
VDSS
VGSS
ID
ID(pulse)Note1
IDR
IAP Note 2
EAR Note 2
Pch Note3
θch-C
Tch
Tstg
Ratings
30
±20
55
220
55
25
62.5
60
2.08
150
–55 to +150
(Ta = 25°C)
Unit
V
V
A
A
A
A
mJ
W
°C/W
°C
°C
REJ03G1638-0400 Rev.4.00 Apr 10, 2008
Page 1 of 6
1 page RJK0329DPB
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3
Normalized Transient Thermal Impedance vs. Pulse Width
Tc = 25°C
1
D=1
0.5
0.3
0.2
0.1 0.1
0.05
0.03
0.02
0.011shot
pulse
0.01
10 µ
100 µ
θch – c (t) = γ s (t) • θch – c
θch – c = 2.09°C/W, Tc = 25°C
PDM
D=
PW
T
PW
T
1m
10 m
100 m
Pulse Width PW (s)
1
10
Vin
15 V
Avalanche Test Circuit
VDS
Monitor
Rg
50 Ω
L
IAP
Monitor
D. U. T
VDD
Avalanche Waveform
EAR =
1
2
L • IAP2 •
VDSS
VDSS – VDD
IAP
ID
V(BR)DSS
VDS
VDD
0
Switching Time Test Circuit
Vin Monitor
Rg
D.U.T.
Vout
Monitor
RL
Vin
10 V
VDS
= 10 V
Switching Time Waveform
90%
Vin
Vout
10%
10%
10%
td(on)
90%
tr
90%
td(off)
tf
REJ03G1638-0400 Rev.4.00 Apr 10, 2008
Page 5 of 6
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet RJK0329DPB.PDF ] |
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