Datenblatt-pdf.com


EN29LV512 Schematic ( PDF Datasheet ) - Eon Silicon Solution

Teilenummer EN29LV512
Beschreibung 512 Kbit (64K x 8-bit ) Uniform Sector
Hersteller Eon Silicon Solution
Logo Eon Silicon Solution Logo 




Gesamt 30 Seiten
EN29LV512 Datasheet, Funktion
www.DataSheet4U.com
E5d1Na220K9.bLiVt 5(1624K x 8-bit ) Uniform Sector,
CMOS 3.0 Volt-only Flash Memory
EN29LV512
FEATURES
Single power supply operation
- Full voltage range: 2.7-3.6 volt read and write
operations for battery-powered applications.
- Regulated voltage range: 3.0-3.6 volt read
and write operations for high performance
3.3 volt microprocessors.
High performance
- Full voltage range: access times as fast as 55
ns
- Regulated voltage range: access times as fast
as 45ns
Low power consumption (typical values at 5
MHz)
- 7 mA typical active read current
- 15 mA typical program/erase current
- 1 µA typical standby current (standard access
time to active mode)
Flexible Sector Architecture:
- Four 16 Kbyte sectors
- Supports full chip erase
- Individual sector erase supported
- Sector protection and unprotection:
Hardware locking of sectors to prevent
program or erase operations within individual
sectors
High performance program/erase speed
- Byte program time: 8µs typical
- Sector erase time: 500ms typical
JEDEC Standard program and erase
commands
JEDEC standard DATA polling and toggle bits
feature
Single Sector and Chip Erase
Embedded Erase and Program Algorithms
Erase Suspend / Resume modes:
Read or program another Sector during
Erase Suspend Mode
triple-metal double-poly triple-well CMOS Flash
Technology
Low Vcc write inhibit < 2.5V
>100K program/erase endurance cycle
Package options
- 8mm x 20mm 32-pin TSOP (Type 1)
- 8mm x 14mm 32-pin TSOP (Type 1)
- 32-pin PLCC
-
Commercial and industrial Temperature Range
GENERAL DESCRIPTION
The EN29LV512 is a 512-Kbit, electrically erasable, read/write non-volatile flash memory, organized
as 65,536 bytes. Any byte can be programmed typically in 8µs. The EN29LV512 features 3.0V
voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT
states in high-performance microprocessor systems.
The EN29LV512 has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable (WE)
controls, which eliminate bus contention issues. This device is designed to allow either single
Sector or full chip erase operation, where each Sector can be individually protected against
program/erase operations or temporarily unprotected to erase or program. The device can sustain a
minimum of 100K program/erase cycles on each Sector.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/01/05






EN29LV512 Datasheet, Funktion
www.DataSheet4U.com
USER MODE DEFINITIONS
EN29LV512
Standby Mode
The EN29LV512 has a CMOS-compatible standby mode, which reduces the current to < 1µA
(typical). It is placed in CMOS-compatible standby when the CE pin is at VCC ± 0.3. The device also
has a TTL-compatible standby mode, which reduces the maximum VCC current to < 1mA. It is
placed in TTL-compatible standby when the CE pin is at VIH. When in standby modes, the outputs
are in a high-impedance state independent of the OE input.
Read Mode
The device is automatically set to reading array data after device power-up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status data. After completing a programming operation in
the Erase Suspend mode, the system may once again read array data with the same exception. See
“Erase Suspend/Erase Resume Commands” for more additional information.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset Command” additional details.
Output Disable Mode
When the CE or OE pin is at a logic high level (VIH), the output from the EN29LV512 is disabled.
The output pins are placed in a high impedance state.
Auto Select Identification Mode
The autoselect mode provides manufacturer and device identification, and sector protection
verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for
programming equipment to automatically match a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can also be accessed in-system through the
command register.
When using programming equipment, the autoselect mode requires VID (11 V) on address pin A9.
Address pins A8, A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when
verifying sector protection, the sector address must appear on the appropriate highest order address
bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the
remaining address bits that are don’t-care. When all necessary bits have been set as required, the
programming equipment may then read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system; the host system can issue the autoselect command via
the command register, as shown in the Command Definitions table. This method does not require
VID. See “Command Definitions” for details on using the autoselect mode.
Write Mode
Write operations, including programming data and erasing sectors of memory, require the host
system to write a command or command sequence to the device. Write cycles are initiated by
placing the byte or word address on the device’s address inputs while the data to be written is input
on DQ[7:0]. The host system must drive the CE# and WE# pins Low and the OE# pin High for a
valid write operation to take place. All addresses are latched on the falling edge of WE# and CE#,
This Data Sheet may be revised by subsequent versions
6
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2004/01/05

6 Page









EN29LV512 pdf, datenblatt
www.DataSheet4U.com
EN29LV512
an attempt to read the device will produce the true data last written to DQ7. For the embedded
Programming, DATA polling is valid after the rising edge of the fourth WE or CE pulse in the four-
cycle sequence.
When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the
DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7
output during the read. For Chip Erase, the DATA polling is valid after the rising edge of the sixth
W E or CE pulse in the six-cycle sequence. For Sector Erase, DATA polling is valid after the last
rising edge of the sector erase W E or C E pulse.
DATA Polling must be performed at any address within a sector that is being programmed or
erased and not a protected sector. Otherwise, DATA polling may give an inaccurate result if the
address used is in a protected sector.
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when
the output enable ( OE ) is low. This means that the device is driving status information on DQ7 at
one instant of time and valid data at the next instant of time. Depending on when the system
samples the DQ7 output, it may read the status of valid data. Even if the device has completed the
embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid.
The valid data on DQ0-DQ7 will be read on the subsequent read attempts.
The flowchart for DATA Polling (DQ7) is shown on Flowchart 5. The DATA Polling (DQ7) timing
diagram is shown in Figure 8.
DQ6: Toggle Bit I
The EN29LV512 provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the
embedded programming and erase operations. (See Table 6)
During an embedded Program or Erase operation, successive attempts to read data from the device
at any address (by toggling OE or CE ) will result in DQ6 toggling between “zero” and “one”. Once
the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be
read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the
rising edge of the fourth WE pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is
valid after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after
the last rising edge of the Sector Erase W E pulse.
In Byte Programming, if the sector being written to is protected, DQ6 will toggles for about 2 µs, then
stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all
selected blocks are protected, DQ6 will toggle for about 100 µs. The chip will then return to the read
mode without changing data in all protected blocks.
Toggling either CE or OE will cause DQ6 to toggle.
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is
shown in Figure 9.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the
program or erase cycle was not successfully completed. Since it is possible that DQ5 can become a
1 when the device has successfully completed its operation and has returned to read mode, the user
must check again to see if the DQ6 is toggling after detecting a “1” on DQ5.
This Data Sheet may be revised by subsequent versions 12 ©2003 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. B, Issue Date: 2004/01/05

12 Page





SeitenGesamt 30 Seiten
PDF Download[ EN29LV512 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
EN29LV512512 Kbit (64K x 8-bit ) Uniform SectorEon Silicon Solution
Eon Silicon Solution

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche