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EN29LV160J Schematic ( PDF Datasheet ) - Eon Silicon Solution

Teilenummer EN29LV160J
Beschreibung 16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory
Hersteller Eon Silicon Solution
Logo Eon Silicon Solution Logo 




Gesamt 44 Seiten
EN29LV160J Datasheet, Funktion
EN29LV160J
www.DatE1a0S6Nh.eMe2t49eUL.gcoVamb1i6t0(J20**4*8*K**PxR8-EbLitIM/ 1IN02A4RKYxD1R6-AbFitT) *F*l*a*s*h* Memory
Boot Sector Flash Memory, CMOS 3.0 Volt-only
FEATURES
3.0V, single power supply operation
- Minimizes system level power requirements
Manufactured on 0.28 µm process technology
High performance
- Access times as fast as 70 ns
Low power consumption (typical values at 5
MHz)
- 7 mA typical active read current
- 15 mA typical program/erase current
- 1 µA typical standby current (standard access
time to active mode)
Flexible Sector Architecture:
- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors (byte mode)
- One 8 Kword, two 4 Kword, one 16 Kword
and thirty-one 32 Kword sectors (word mode)
- Supports full chip erase
- Individual sector erase supported
- Sector protection:
Hardware locking of sectors to prevent
program or erase operations within individual
sectors
Additionally, temporary Sector Group
Unprotect allows code changes in previously
locked sectors.
High performance program/erase speed
- Byte program time: 8µs typical
- Sector erase time: 200ms typical
- Chip erase time: 3.5s typical
JEDEC Standard program and erase
commands
JEDEC standard DATA polling and toggle
bits feature
Single Sector and Chip Erase
Sector Unprotect Mode
Embedded Erase and Program Algorithms
Erase Suspend / Resume modes:
Read and program another Sector during
Erase Suspend Mode
0.28 µm double-metal double-poly
triple-well CMOS Flash Technology
Low Vcc write inhibit < 2.5V
>100K program/erase endurance cycle
48-pin TSOP (Type 1)
Commercial Temperature Range
GENERAL DESCRIPTION
The EN29LV160J is a 16-Megabit, electrically erasable, read/write non-volatile flash memory,
organized as 2,097,152 bytes or 1,048,576 words. Any byte can be programmed typically in 10µs.
The EN29LV160J features 3.0V voltage read and write operation, with access times as fast as 55ns
to eliminate the need for WAIT states in high-performance microprocessor systems.
The EN29LV160J has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable (WE)
controls, which eliminate bus contention issues. This device is designed to allow either single Sector
or full chip erase operation, where each Sector can be individually protected against program/erase
operations or temporarily unprotected to erase or program. The device can sustain a minimum of
100K program/erase cycles on each Sector.
4800 Great America Parkway, Suite 202
1
Santa Clara, CA 95054
Rev 0.3 Release Date: 2002/01/30
Tel: 408-235-8680
Fax: 408-235-8685






EN29LV160J Datasheet, Funktion
PRODUCT SELECTOR GUIDE
www.DataSheet4U.com
Product Number
Speed Option Regulated Voltage Range: Vcc=3.0 – 3.6 V
Full Voltage Range: Vcc=2.7 – 3.6 V
Max Access Time, ns (tacc)
Max CE# Access, ns (tce)
Max OE# Access, ns (toe)
EN29LV160J
EN29LV160J
-70 -
- -90
70 90
70 90
30 35
BLOCK DIAGRAM
RY/BY
Vcc
Vss
State
Control
WE
Command
Register
CE
OE
Vcc Detector
A0-A18
Block Protect Switches
Erase Voltage Generator
DQ0-DQ15 (A-1)
Input/Output Buffers
Program Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data Latch
Timer
Y-Decoder
STB
X-Decoder
Y-Gating
Cell Matrix
4800 Great America Parkway, Suite 202
6
Santa Clara, CA 95054
Rev 0.3 Release Date: 2002/01/30
Tel: 408-235-8680
Fax: 408-235-8685

6 Page









EN29LV160J pdf, datenblatt
EN29LV160J
Hardware Data protection
www.DataSheet4U.com
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which might
otherwise be caused by false system level signals during Vcc power up and power down transitions, or
from system noise.
Low VCC Write Inhibit
When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc
power up and power down. The command register and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The system must
provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than
VLKO.
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on OE , CE or W E do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE = VIL, CE = VIH, or W E = VIH. To initiate a write
cycle, CE and W E must be a logical zero while OE is a logical one. If CE , W E , and OE are all
logical zero (not recommended usage), it will be considered a read.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with CE = VIL, W E = VIL and OE = VIH, the device will not accept commands on the rising edge of
WE.
4800 Great America Parkway, Suite 202
12
Santa Clara, CA 95054
Rev 0.3 Release Date: 2002/01/30
Tel: 408-235-8680
Fax: 408-235-8685

12 Page





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