|
|
Teilenummer | DS1845 |
|
Beschreibung | Dual NV Potentiometer and Memory | |
Hersteller | Dallas Semiconductor | |
Logo | ||
Gesamt 13 Seiten www.DataSheet4U.com
DS1845
Dual NV Potentiometer and Memory
www.dalsemi.com
FEATURES
Two linear taper potentiometers
− DS1845-010 one 10k, 100 position &
one 10k, 256 position
− DS1845-050 one 10k, 100 position &
one 50k, 256 postition
− DS1845-100 one 10k, 100 position &
one 100k, 256 position
256 bytes of EEPROM memory
Access to data and potentiometer control via
a 2-wire interface
External Write Enable pin to protect data and
potentiometer settings
Nonvolatile wiper storage in 2 bytes of
address space
Operates from 3V or 5V supplies
Packaging: Flip Chip Package, 16-ball
STPBGA, 14-pin TSSOP
Industrial operating temperature: -40ºC to
+85ºC
Programming temperature: 0ºC to +70ºC
PIN ASSIGNMENT
SDA
SCL
A0
A1
A2
WP
GND
1
2
3
4
5
6
7
14 Vcc
13 H0
12 W1
11 H1
10 L1
9 W0
8 L0
14-Pin TSSOP (173 mil)
14-Pin Flip Chip (100 x 100 mils)
16-BALL STPBGA (4 x 4 mm)
See Mech. Drawing Section
PIN DESCRIPTION
VCC
GND
- 3V or 5V Power Supply Input
- Ground
SDA
- 2-wire Serial Data
Input/Output
SCL - 2-wire Serial Clock Input
WP - Write Protect Input
A0, A1, A2 - Address Inputs
H0, H1
- High-End of Potentiometer
L 0, L1
- Low-End of Potentiometer
W0, W1
- Wiper Terminal of
Potentiometer
DESCRIPTION
The DS1845 Dual NV Potentiometer and Memory consists of one=100-position linear taper
potentiometer, one=256-position linear taper potentiometer, 256 bytes of EEPROM memory, and a 2-wire
interface. The device provides an ideal method for setting bias voltages and currents in control
applications using a minimum of circuitry. The EEPROM memory allows a user to store configuration
or calibration data for a specific system or device as well as provide control of the potentiometer wiper
settings. Any type of user information may reside in the first 248 bytes of this memory. The next two
addresses of EEPROM memory are for potentiometer settings and the remaining 6 bytes of memory are
reserved. These reserved and potentiometer registers should not be used for data storage. Access to this
EEPROM is via an industry standard 2-wire bus. The interface I/O pins consist of SDA and SCL. The
wiper position of the DS1845, as well as EEPROM data, can be hardware write-protected using the Write
Protect (WP) input pin.
1 of 13
051900
DS1845
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line can be changed
durwinwgw.DthateaSLheOetW4U.cpoemriod of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3
detail how data transfer is accomplished on the two-wire bus. Depending upon the state of the R/W bit,
two types of data transfer are possible.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a 9th
bit.
Within the bus specifications a regular mode (100 kHz clock rate) and a fast mode (400 kHz clock rate)
are defined. The DS1845 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is a stable LOW during the HIGH period of the acknowledge related clock pulse.
Of course, setup and hold times must be taken into account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
1. Data transfer from a master transmitter to a slave receiver. The 1st byte transmitted by the master is
the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge bit
after each received byte.
2. Data transfer from a slave transmitter to a master receiver. The master transmits the 1st byte (the
command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a
number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit
after all received bytes other than the last byte. At the end of the last received byte, a ‘not
acknowledge’ can be returned.
The master device generates all serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START condition. Since a repeated START condition is
also the beginning of the next serial transfer, the bus will not be released.
6 of 13
6 Page DS1845
6. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period
wowfwt.DhaetaSSCheLet4sUig.cnomal. If such a device does stretch the LOW period of the SCL signal, it must output the
next data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 = 1250 ns before the SCL line is
released.
7. After this period, the first clock pulse is generated.
8. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of
the SCL signal.
9. CB - total capacitance of one bus line in picofarads, timing referenced to (0.9(VCC) and (0.1)(VCC).
10. EEPROM write begins after a stop condition occurs.
11. Resistor inputs can not go beneath GND by more than 0.5V or above VCC by more that 0.5V.
12. The –3 dB cutoff frequency for the DS1845 is 1 MHz (10k/10k version).
13. Absolute linearity is used to measure expected wiper voltage as determined by wiper position. The
DS1845 is specified to provide an absolute linearity of ± 0.5 LSB (10k/10k version), ±1 LSB(10k/50k
version), and ± 1.5 LSB (10k/100k) version.
14. Relative linearity is used to determine the change of wiper voltage between two adjacent wiper
positions. The DS1845 is specified to have a relative linearity of ± 0.25 dB.
15. When used as a rheostat or variable resister the temperature coefficient applies: 650 ppm/°C. When
used as a voltage divider or potentiometer, the effective temperature coefficient approaches
30 ppm/°C.
16. ICC specified with SDA pin open.
17. Maximum Icc is dependent on clock rates.
18. Valid for VCC = 5V only.
19. Valid at 25°C only.
12 of 13
12 Page | ||
Seiten | Gesamt 13 Seiten | |
PDF Download | [ DS1845 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
DS1841 | Temperature-Controlled | Maxim Integrated Products |
DS1842 | Bias Output Stage | Maxim Integrated Products |
DS1842A | Bias Output Stage | Maxim Integrated Products |
DS1843 | RSSI Burst-Mode Sample-and-Hold Circuit | Maxim Integrated Products |
DS1844 | Quad Digital Potentiometer | Dallas Semiconductor |
Teilenummer | Beschreibung | Hersteller |
CD40175BC | Hex D-Type Flip-Flop / Quad D-Type Flip-Flop. |
Fairchild Semiconductor |
KTD1146 | EPITAXIAL PLANAR NPN TRANSISTOR. |
KEC |
www.Datenblatt-PDF.com | 2020 | Kontakt | Suche |