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PDF ADC08D1520 Data sheet ( Hoja de datos )
| Número de pieza | ADC08D1520 | |
| Descripción | Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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April 7, 2008
www.DataSheet4U.com
ADC08D1520
Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D
Converter
General Description
The ADC08D1520 is a dual, low power, high performance
CMOS analog-to-digital converter that builds upon the
ADC08D1500 platform. The ADC08D1520 digitizes signals to
8 bits of resolution at sample rates up to 1.7 GSPS. It has
expanded features compared to the ADC08D1500, which in-
clude a test pattern output for system debug, a clock phase
adjust, and selectable output demultiplexer modes. Consum-
ing a typical 1.6 Watts in Non-Demultiplex Mode at 1.0 GSPS
from a single 1.9 Volt supply, this device is guaranteed to have
no missing codes over the full operating temperature range.
The unique folding and interpolating architecture, the fully dif-
ferential comparator design, the innovative design of the in-
ternal sample-and-hold amplifier and the self-calibration
scheme enable a very flat response of all dynamic parameters
beyond Nyquist, producing a high 7.4 Effective Number of Bits
(ENOB) with a 748 MHz input signal and a 1.5 GHz sample
rate while providing a 10-18 Code Error Rate (C.E.R.) Output
formatting is offset binary and the Low Voltage Differential
Signaling (LVDS) digital outputs are compatible with IEEE
1596.3-1996, with the exception of an adjustable common
mode voltage between 0.8V and 1.2V.
Each converter has a selectable output demultiplexer which
feeds two LVDS buses. If the 1:2 Demultiplexed Mode is se-
lected, the output data rate is reduced to half the input sample
rate on each bus. When Non-Demultiplexed Mode is select-
ed, the output data rate on channels DI and DQ is at the same
rate as the input sample clock. The two converters can be
interleaved and used as a single 3 GSPS ADC.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a leaded or lead-free,
128-pin, thermally enhanced, exposed pad, LQFP and oper-
ates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature
range.
Features
■ Single +1.9V ±0.1V Operation
■ Interleave Mode for 2x Sample Rate
■ Multiple ADC Synchronization Capability
■ Adjustment of Input Full-Scale Range, Clock Phase, and
Offset
■ Choice of SDR or DDR Output Clocking
■ 1:1 or 1:2 Selectable Output Demux
■ Second DCLK Output
■ Duty Cycle Corrected Sample Clock
■ Test pattern
Key Specifications
■ Resolution
■ Max Conversion Rate
■ Code Error Rate
■ ENOB @ 748 MHz Input
■ DNL
■ Power Consumption (Non-DES Mode)
— Operating in Non-demux Mode
— Operating in 1:2 Demux Mode
— Power Down Mode
8 Bits
1.5 GSPS (max)
10-18 (typ)
7.4 Bits (typ)
±0.15 LSB (typ)
1.6 W (typ)
2.0 W (typ)
3.5 mW (typ)
Applications
■ Direct RF Down Conversion
■ Digital Oscilloscopes
■ Satellite Set-top boxes
■ Communications Systems
■ Test Instrumentation
Ordering Information
Industrial Temperature Range (-40°C < TA < +85°C)
ADC08D1520CIYB
ADC08D1520CIYB/NOPB
ADC08D1520DEV
NS Package
Leaded 128-Pin Exposed Pad LQFP
Lead-free 128-Pin Exposed Pad LQFP
Development Board
© 2008 National Semiconductor Corporation 201931
www.national.com
1 page  
Pin Functions
Pin No.
Symbol
www.DataSheet4U.com
14
FSR/ALT_ECE/
DCLK_RST-
127 CalDly / DES / SCS
18 CLK+
19 CLK-
Equivalent Circuit
Description
Full Scale Range Select, Alternate Extended Control Enable
and DCLK_RST-. This pin has three functions. It can
conditionally control the ADC full-scale voltage, enable the
Extended Control Mode, or become the negative polarity
signal of a differential pair in differential DCLK_RST mode.
If pin 52 is floating or at logic high and pin 41 is floating, this
pin can be used to set the full-scale-range or can be used as
an alternate Extended Control Mode enable pin. When used
as the FSR pin, a logic low on this pin sets the full-scale
differential input range to a reduced VIN input level . A logic
high on this pin sets the full-scale differential input range to
a higher VIN input level. See Converter Electrical
Characteristics. To enable the Extended Control Mode,
whereby the serial interface and control registers are
employed, allow this pin to float or connect it to a voltage
equal to VA/2. See 1.2 NON-EXTENDED AND EXTENDED
CONTROL MODE for information on the Extended Control
Mode. Note that pin 41 overrides the Extended Control Mode
enable of this pin. When pin 52 is held at logic low, this pin
acts as the DCLK_RST- pin. When in differential DCLK_RST
mode, there is no pin-controlled FSR and the full-scale-range
is defaulted to the higher VIN input level.
Calibration Delay, Dual Edge Sampling and Serial Interface
Chip Select. In non-extended control mode, this pin functions
as the Calibration Delay select. A logic high or low the
number of input clock cycles after power up before
calibration begins (See 1.1.1 Calibration). When this pin is
floating or connected to a voltage equal to VA/2, DES (Dual
Edge Sampling) Mode is selected where the I-channel is
sampled at twice the input clock rate and the Q-channel is
ignored. See 1.1.5.1 Dual-Edge Sampling. In extended
control mode, this pin acts as the enable pin for the serial
interface input and the CalDly value becomes "0" (short
delay with no provision for a long power-up calibration delay).
Differential clock input pins for the ADC. The differential clock
signal must be a.c. coupled to these pins. The input signal is
sampled on the falling edge of CLK+. See 1.1.2 Acquiring
the Input for a description of acquiring the input and 2.3 THE
CLOCK INPUTS for an overview of the clock inputs.
10 VINI-
11 VINI+
22 VINQ+
23 VINQ−
Analog signal inputs to the ADC. The differential full-scale
input range of this input is programmable using the FSR pin
14 in Non-Extended Control Mode and the Input Full-Scale
Voltage Adjust register in the Extended Control Mode. Refer
to the VIN specification in the Converter Electrical
Characteristics for the full-scale input range in the Non-
Extended Control Mode. Refer to 1.4 REGISTER
DESCRIPTION for the full-scale input range in the Extended
Control Mode.
5 www.national.com
5 Page 
Symbol
Parameter
Analog Input Capacitance,
www.DNaotarmShael eotp4eUr.actoiomn
CIN (Notes 10, 11)
Analog Input Capacitance,
DES Mode (Notes 10, 11)
Conditions
Differential
Each input pin to ground
Differential
Each input pin to ground
Typical
(Note 8)
0.02
1.6
0.08
2.2
RIN Differential Input Resistance
ANALOG OUTPUT CHARACTERISTICS
100
VCMO
Common Mode Output Voltage ICMO = ±100 µA
TC VCMO
Common Mode Output Voltage
Temperature Coefficient
TA = −40°C to +85°C
VCMO_LVL
CLOAD VCMO
VCMO input threshold to set D.C. VA = 1.8V
Coupling mode
VA = 2.0V
Maximum VCMO Load
Capacitance
VBG
Bandgap Reference Output
Voltage
IBG = ±100 µA
TC VBG
CLOAD VBG
Bandgap Reference Voltage
Temperature Coefficient
TA = −40°C to +85°C,
IBG = ±100 µA
Maximum Bandgap Reference
load Capacitance
CHANNEL-TO-CHANNEL CHARACTERISTICS
Offset Match
Positive Full-Scale Match
Zero offset selected in Control Register
Negative Full-Scale Match
Zero offset selected in Control Register
X-TALK
Phase Matching (I, Q)
Crosstalk from I-channel
(Aggressor) to Q-channel
(Victim)
fIN = 1.5 GHz
Aggressor = 867 MHz F.S.
Victim = 100 MHz F.S.
X-TALK
Crosstalk from Q-channel
(Aggressor) to I-channel
(Victim)
Aggressor = 867 MHz F.S.
Victim = 100 MHz F.S.
LVDS CLK INPUT CHARACTERISTICS (Typical specs also apply to DCLK_RST)
1.26
118
0.60
0.66
1.26
28
1
1
1
<1
−65
−65
Sine Wave Clock
VID Differential Clock Input Level
Square Wave Clock
0.6
0.6
VOSI
Input Offset Voltage
CIN
Input Capacitance
(Notes 10, 11)
Differential
Each input to ground
DIGITAL CONTROL PIN CHARACTERISTICS
OutV, DCLK_RST, PD, PDQ, CAL, ECE,
VIH
Logic High Input Voltage
DRST_SEL
OutEdge, FSR, CalDly
OutV, DCLK_RST, PD, PDQ, CAL
VIL
Logic Low Input Voltage
OutEdge, FSR, CalDly, ECE, DRST_SEL
CIN
Input Capacitance
(Notes 11, 13)
Each input to ground
1.2
0.02
1.5
1.2
Limits
(Note 8)
94
106
0.95
1.45
80
1.20
1.33
80
0.4
2.0
0.4
2.0
0.69 x VA
0.79 x VA
0.28 x VA
0.21 x VA
Units
(Limits)
pF
pF
pF
pF
Ω (min)
Ω (max)
V (min)
V (max)
ppm/°C
V
V
pF
V (min)
V (max)
ppm/°C
pF
LSB
LSB
LSB
Degree
dB
dB
VP-P (min)
VP-P (max)
VP-P (min)
VP-P (max)
V
pF
pF
V (min)
V (min)
V (max)
V (max)
pF
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| Páginas | Total 44 Páginas | |
| PDF Descargar | [ Datasheet ADC08D1520.PDF ] | |
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