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Número de pieza | RCLAMP0504S | |
Descripción | TVS Array | |
Fabricantes | Semtech Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de RCLAMP0504S (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
No Preview Available ! PROwwTwE.DCaTtaISOheNet4UP.cRomODUCTS - RailClamp
Description
RailClamps are surge rated diode arrays designed to
protect high speed data interfaces. This series has
been specifically designed to protect sensitive compo-
nents which are connected to data and transmission
lines from overvoltage caused by ESD (electrostatic
discharge), CDE (Cable Discharge Events), and EFT
(electrical fast transients).
The unique design incorporates surge rated, low
capacitance steering diodes and a TVS diode in a
single package. During transient conditions, the
steering diodes direct the transient to either the
positive side of the power supply line or to ground. The
internal TVS diode prevents over-voltage on the power
line, protecting any downstream components.
The low capacitance array configuration allows the user
to protect four high-speed data or transmission lines.
The low inductance construction minimizes voltage
overshoot during high current surges. This device is
optimized for ESD protection of portable electronics.
They may be used to meet the ESD immunity require-
ments of IEC 61000-4-2, Level 4 (±15kV air, ±8kV
contact discharge).
RClamp0504S
RailClamp
Low Capacitance TVS Array
Features
Transient protection for high-speed data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
Array of surge rated diodes with internal TVS Diode
Small package saves board space
Protects up to four I/O lines & power line
Low capacitance (<3pF) for high-speed interfaces
No insertion loss to 2.0GHz
Low leakage current and clamping voltage
Low operating voltage: 5.0V
Solid-state silicon-avalanche technology
Mechanical Characteristics
JEDEC SOT-23 6L package
Nominal Dimensions: 2.9x2.8mm
RoHS/WEEE Compliant
Molding compound flammability rating: UL 94V-0
Marking: Marking Code
Packaging: Tape and Reel
Applications
USB 2.0
USB OTG
Monitors and Flat Panel Displays
Digital Visual Interface (DVI)
Gigabit Ethernet
IEEE 1394 Firewire Ports
Circuit Diagram
Schematic & PIN Configuration
5
13
46
2
Revision 01/17/2008
1
SOT-23 6L (Top View)
www.semtech.com
1 page RClamp0504S
PROTECTION PRODUCTS
Appwlwiwc.aDatitaoSnheset4IUn.cfoomrmation
Device Connection Options for Protection of Four
High-Speed Data Lines
This device is designed to protect data lines by
clamping them to a fixed reference. When the voltage
on the protected line exceeds the reference voltage
the steering diodes are forward biased, conducting the
transient current away from the sensitive circuitry.
Data lines are connected at pins 1, 3, 4 and 6. Pin 2
should be connected directly to a ground plane. The
path length is kept as short as possible to minimize
parasitic inductance.
The positive reference is connected at pin 5. The
options for connecting the positive reference are as
follows:
1. To protect data lines and the power line, connect
pin 5 directly to the positive supply rail (VCC). In this
configuration the data lines are referenced to the
supply voltage. The internal TVS diode prevents
over-voltage on the supply rail.
2. In applications where the supply rail does not exit
the system, the internal TVS may be used as the
reference. In this case, pin 5 is not connected.
The steering diodes will begin to conduct when the
voltage on the protected line exceeds the working
voltage of the TVS (plus one diode drop).
3. In applications where complete supply isolation is
desired, the internal TVS is again used as the
reference and VCC is connected to one of the I/O
inputs. An example of this configuration is the
protection of a SIM port. The Clock, Reset, I/O,
and VCC lines are connected at pins 1, 3, 4, and 6.
Pin 2 is connected to ground and pin 5 is not
connected.
Protection of Four Data Lines and Power Supply Line
Protection of Four Data Lines Using Internal TVS
Diode as Reference
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small com-
pared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
2008 Semtech Corp.
5
www.semtech.com
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet RCLAMP0504S.PDF ] |
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