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EDGE6420 Schematic ( PDF Datasheet ) - Semtech Corporation

Teilenummer EDGE6420
Beschreibung Per-Pin Electronics Companion DAC
Hersteller Semtech Corporation
Logo Semtech Corporation Logo 




Gesamt 29 Seiten
EDGE6420 Datasheet, Funktion
HIGwHw-wP.DEatRaSFheOetR4UM.coAmNCE PRODUCTS – ATE
Description
Features
Edge6420
Per-Pin Electronics
Companion DAC
The Edge6420 is a monolithic device which has 64
integrated DACs that are designed specifically for all per
channel wide-voltage and current levels needed for pin
electronics inside automatic test equipment. The chip
can also be used for other applications requiring multiple
integrated voltage or current DAC outputs.
Voltage DACs
• Wide voltage (17V range)
• Adjustable full scale range
• Adjustable minimum output
• 13 bits resolution
Current DACs
• ~3.6 mA full scale range
• Adjustable full scale range
• 6/13 bits resolution
64 Total DACs/Package Including:
• Wide Voltage Output Range (17V Range); Useful
for Supervoltage
• 44 Voltage DACs / Package
• 20 Current DACs / Package
• Adjustable Full Scale Range
• Adjustable Output Voltage Offset
• Small 13x13mm BGA Package
• All DACs are Guaranteed Monotonic
Applications
• Test Equipment
• Applications requiring multiple programmable
voltage and currents
The DACs are programmed using a serial interface.
The inclusion of 64 total DACs into 1 package offers an
extremely high density, flexible solution normally
implemented using multiple components.
Functional Block Diagram
SDI
CE
CK
UPDATE
RESET*
DAC 0
DAC 63
Channel 0
VOUT_CH0_[0:10]
IOUT_CH0_[0:4]
Channel 1
VOUT_CH1_[0:10]
IOUT_CH1[0:4]
Channel 2
VOUT_CH2_[0:10]
IOUT_CH2_[0:4]
Channel 3
VOUT_CH3_[0:10]
IOUT_CH3_[0:4]
SDO CK_OUT
Revision 4 / April 29, 2002
1
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EDGE6420 Datasheet, Funktion
Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Circwuwwit.DDataeSshecert4ipU.tcioomn
Chip Overview
Grouping of DACs
The Edge6420 provides 64 output levels (44 voltage and
20 current). These outputs can easily be configured to
generate the specific analog voltage and current
requirements for 4 channels of ATE pin electronics
including:
3 level driver
Window comparator
Active load
Per pin PMU
without requiring any scaling or shifting via external
components.
DACs are separated into 4 channels of 6 distinct functional
groups. Groups are defined by:
Type (voltage or current output)
Resolution (# of bits)
Output range
Output compliance.
Table 1 defines the DACs on a per channel basis:
The Edge6420 has the flexibility to be used in other
configurations for other applications.
Programming of the chip is done using a 4 bit digital
interface comprised of:
Serial Data In
Clock
Update
Chip Enable.
Attribute
Total # of
DACs in Group
Type
Resolution
(# of bits)
Output Range:
Max DAC Range (Note 1)
Offset Range
Group
A
5 per channel
V
13
11.5V
-3.5V to 2.5V
Group
B
2 per channel
V
13
11.5V
-3.5V to 2.5V
Group
C
2 per channel
V
13
17V
-3.5V to 2.5V
Group
D
2 per channel
V
13
11.5V
-3.5V to 2.5V
Group
E
2 per channel
I
13
3.6 mA
128 LSB
(Note 2)
Group
F
3 per channel
I
6
3.6 mA
0
Adjustable Output Offset yes yes yes yes
no
no
Compliance
±100 µA
±100 µA
±100 µA
±100 µA
0.2 to AVDD 2.2V 0.2 to AVDD 2.2V
(Note 3)
(Note 3)
Note 1:
Note 2:
Note 3:
The max DAC range is achieved through specific AVCC, AVEE, and Gain resistor settings. See the
equations in the "DAC Voltage Output Overview", "DAC Current Output Overview", and specifications for details.
128 LSB is equivalent to 128 * LSB, where LSB = Range / 213. For max range case of 3.6 mA,
this offset would thus be: 56.26 µA of offset current at Code 0.
Compliance specified in the table is at IOUT = 1.3mA. Maximum compliance is lower at higher currents.
Please refer to specifications for compliance at other output currents.
Table 1. DAC Grouping
2000 Semtech Corp.
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EDGE6420 pdf, datenblatt
Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
Circwuwwit.DDataeSshecert4ipU.tcioomn (continued)
Programming Sequence
The DACs are programmed serially (see Figures 1, 2a,
2b, and 3). On each rising edge of CK, SDI is loaded into
a shift register. It requires 24 Clocks to fully load the shift
register (8 address bits + 16 data bits).
For Groups A, B, C, D, and E DACs:
Group F uses only 6 bits, and these bits must be
programmed as shown in Figure 2b. 24 clock cycles are
required for programming, with A0 loaded on the first rising
CK edge, and D8 (as shown in Figure 2b) loaded on the
24th rising CK edge.
As is the case with other groups, a 24th falling edge of
CK24 is required for proper programming of Group F DACs.
Address and data are loaded LSB first, MSB last. In a 24
clock sequence, A0, as shown in Figure 2a, is loaded into
the shift register on the first CK rising edge, and D15 is
loaded last on the 24th rising CK edge. Note that a 24th
falling CK edge is required to transfer the data from the
Central DAC Latch to the selected DAC latch (See Figure
1). See detailed Timing Diagrams in the "AC
Characteristics" specifications section.
Chip Enable
CE is a synchronous input which determines whether the
Central DAC latch shown in Figure 1 is loaded with data
from the shift register. CE is also necessary to update a
DAC. If CE is high, rising edges of CK load data from the
shift register to an internal latch. If CE is low, central DAC
latch updating is disabled.
For Group F DACs:
The loading sequence is the same as Groups A-E, but
CE
low
high
Central and Individual DAC Latch "Load" Status
Central and individual DAC latch loading is
disabled
Central and individual DAC latches are loaded
DATA
ADDRESS
SDI
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0
MSB
LSB MSB
LSB
Bits reserved for
future upgradability
Bits reserved for
future upgradability
Figure 2a. Format of Address and Data in Shift Register for Group A, B, C, D, and E DACs (13-bits)
DATA
"Don't Care" bits that must be
included in programming sequence
ADDRESS
SDI
D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X A7 A6 A5 A4 A3 A2 A1 A0
MSB
LSB
MSB
LSB
Bits reserved for
future upgradability
Bits reserved for
future upgradability
Figure 2b. Format of Address and Data in Shift Register for Group F DACs (6-bits)
LSB
Addr.
MSB
Addr.
LSB
Data
MSB
Data
Next Set
of Data
SDI
A0 A1
A6 A7 D0 D1
D14 D15
A0
A1
CK
CE
UPDATE
SDO
2000 Semtech Corp.
CK1
TCK
CK24
Previous Data
Update Selected
DAC Register
A0
A1
Corresponds to
A0 loaded at CK1
Figure 3. Serial Data Programming Sequence
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