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PDF ACS8530 Data sheet ( Hoja de datos )
| Número de pieza | ACS8530 | |
| Descripción | Synchronous Equipment Timing Source | |
| Fabricantes | Semtech Corporation | |
| Logotipo |  |
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ACS8530 SETS
Synchronous Equipment Timing Source for
Stratum 2/3E Systems
ADVANCED COMMUNICATIONS
Deswcwrwi.pDattiaoSnheet4U.com
FINAL
Features
DATASHEET
The ACS8530 is a highly integrated, single-chip solution
for the Synchronous Equipment Timing Source (SETS)
function in a SONET or SDH Network Element. The device
generates SONET or SDH Equipment Clocks (SEC) and
Frame Synchronization clocks. The ACS8530 is fully
compliant with the required international specifications
and standards.
The device supports Free-run, Locked and Holdover
modes. It also supports all three types of reference clock
source: recovered line clock, PDH network, and node
synchronization. The ACS8530 generates independent
SEC and BITS clocks, an 8 kHz Frame Synchronization
clock and a 2 kHz Multi-Frame Synchronization clock.
Two ACS8530 devices can be used together in a Master/
Slave configuration mode allowing system protection
against a single ACS8530 failure.
A microprocessor port is incorporated, providing access to
the configuration and status registers for device setup
and monitoring. The ACS8530 supports IEEE 1149.1[5]
JTAG boundary scan.
Block Diagram
Suitable for Stratum 2, 3E, 3, 4E and 4 and SONET
Minimum Clock (SMC) or SONET/SDH Equipment
Clock (SEC) applications (to Telcordia 1244-CORE[19]
Stratum 3E, and GR-253[17], and ITU-T G.812[10]
Type III and G.813[11] specifications)
Accepts 14 individual input reference clocks, all with
robust input clock source quality monitoring
Simultaneously generates nine output clocks, plus
two sync pulse outputs
Absolute Holdover accuracy better than 3 x 10-10
(manual), 7.5 x 10-14 (instantaneous); Holdover
stability defined by choice of external XO
Programmable PLL bandwidth, for wander and jitter
tracking/attenuation, 0.5 mHz to 70 Hz in 18 steps
Automatic hit-less source switchover on loss of input
Phase Transient Protection and Phase Build-out on
locked to reference and on reference switching
Microprocessor interface - Intel, Motorola, Serial,
Multiplexed, or boot from EPROM
Output phase adjustment in 6 ps steps up to ±200 ns
IEEE 1149.1 JTAG[5] Boundary Scan
Single 3.3 V operation. 5 V tolerant
Available in LQFP 100 package
Lead (Pb) - free version available (ACS8530T), RoHS
and WEEE compliant.
Figure 1 Block Diagram of the ACS8530 SETS
2 x AMI
10 x TTL
2 x PECL/LVDS
Programmable;
64/8 kHz (AMI)
2 kHz
4 kHz
N x 8 kHz
1.544/2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
Input
Port
Monitors
and
Selection
Control
14 x SEC
T4 DPLL/Freq. Synthesis
T4
Selector
Optional
Divider, 1/n
n = 1 to 214
PFD
Digital
Loop
Filter
DTO
T0
Selector
T0 DPLL/Freq. Synthesis
Optional
Divider, 1/n
n = 1 to 214
PFD
Digital
Loop
Filter
DTO
TCK
TDI
TMS
TRST
TDO
IEEE
1149.1
JTAG
Chip
Clock
Generator
Priority Register Set
Table
OCXO
Revision 3.02/November 2005 © Semtech Corp.
Microprocessor
Port
Page 1
T4 APLL
Frequency
Dividers
T0 APLL
(output)
Frequency
Dividers
TO APLL
(feedback)
Output
Ports
TO1
to
TO7
TO8
&
TO9
TO10
&
TO11
Outputs
T01-TO7:
E1/DS1 (2.048/
1.544 MHz)
and frequency
multiples:
1.5 x, 2 x, 3 x
4 x, 6 x, 12 x
16 x and 24 x
E3/DS3
2 kHz
8 kHz
and OC-N* rates
T08: AMI
TO9: E1/DS1
TO10: 8 kHz
(FrSync)
TO11: 2 kHz
(MFrSync)
OC-N* rates =
OC-1 51.84 MHz
OC-3 155.52 MHz
and derivatives:
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
F8530D_001BLOCKDIA_09
www.semtech.com
1 page  
ACS8530 SETS
ADVANCED COMMUNICATIONS
PinwDwwe.DsactarSipheteito4Un.com
Table 1 Power Pins
Pin Number
Symbol
12, 13,
16
VD1+, VD3+,
VD2+
26 VAMI+
33, VDD_DIFFa,
39 VDD_DIFFb
44 VDD5
I/O
P
P
P
P
Type
-
-
-
-
50, 61,
85, 86
6
19, 91
11, 14,
15,
49, 62,
84, 87
29
32,
38
1, 5,
20, 92
VDDa, VDDd,
VDDc, VDDb
VA1+
VA2+, VA3+
DGND1, DGND3,
DGND2,
DGNDa, DGNDd,
DGNDc, DGNDb
GND_AMI
GND_DIFFa,
GND_DIFFb
AGND, AGND1,
AGND2, AGND3
P
P
P
P
P
P
P
P
-
-
-
-
-
-
-
-
FINAL
DATASHEET
Description
Supply Voltage: Digital supply to gates in analog section, +3.3 Volts
±10%.
Supply Voltage: Digital supply to AMI output, +3.3 Volts ±10%.
Supply Voltage: Digital supply for differential ports, +3.3 Volts ±10%.
Digital Supply for +5 Volts Tolerance to Input Pins. Connect to +5 Volts
(±10%) for clamping to +5 Volts. Connect to VDD for clamping to
+3.3 Volts. Leave floating for no clamping, input pins tolerant up to
+5.5 Volts.
Supply Voltage: Digital supply to logic, +3.3 Volts ±10%.
Supply Voltage: Analog supply to clock multiplying PLL, +3.3 Volts ±10%.
Supply Voltage: Analog supply to output PLLs, +3.3 Volts ±10%.
Supply Ground: Digital ground for components in PLLs.
Supply Ground: Digital ground for logic.
Supply Ground: Digital ground for AMI output.
Supply Ground: Digital ground for differential ports.
Supply Ground: Analog grounds.
Note...I = Input, O = Output, P = Power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor.
Table 2 Internally Connected
Pin Number
Symbol
3, 4, 17, 22, IC1, IC2, IC3, IC4,
96, 97, 98 IC5, IC6, IC7
I/O
-
Type
-
Description
Internally Connected: Leave to Float.
Revision 3.02/November 2005 © Semtech Corp.
Page 5
www.semtech.com
5 Page 
ACS8530 SETS
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
wwwf.rDeaqtauSehneecty4Uto.co8mkHz, the post-division frequency.
(XX = “Leaky Bucket” ID for this input).
PECL/LVDS/AMI Input Port Selection
The choice of PECL or LVDS compatibility is programmed
(ii) To achieve 8 kHz, the 10 MHz input must be
divided by 1,250. So, if DivN, = 250 = (N+1)
then N must be set to 1,249. This is done by
writing 4E1 hex (1,249 dec to the DivN register
via the cnfg_differential_inputs register, Reg. 36. Unused
PECL differential inputs should be fixed with one input
High (VDD) and the other input Low (GND), or set in LVDS
mode and left floating, in which case one input is
internally pulled High and the other Low.
pair Reg. 46/47.
An AMI port supports a composite clock, consisting of a
Direct Lock Mode 155 MHz.
The max frequency allowed for phase comparison is
77.76 MHz, so for the special case of a 155 MHz input set
to Direct Lock Mode, there is a divide-by-two function
automatically selected to bring the frequency down to
64 kHz AMI clock with 8 kHz boundaries marked by
deliberate violations of the AMI coding rules, as specified
in ITU recommendation G.703[6]. Departures from the
nominal pattern are detected within the ACS8530, and
may cause reference-switching if too frequent. See
section DC Characteristics: AMI Input/Output Port, for
more details. If the AMI port is unused, the pins (I1 and I2)
within the limits of operation.
should be tied to GND.
Table 4 Input Reference Source Selection and Priority Table
Port Number Channel
Number (Bin)
Input Port
Technology
Frequencies Supported
Default
Priority
I1
0001
AMI
64/8 kHz (composite clock, 64 kHz + 8 kHz)
Default (SONET): 64/8 kHz Default (SDH): 64/8 kHz
2
I2
0010
AMI
64/8 kHz (composite clock, 64 kHz + 8 kHz)
Default (SONET): 64/8 kHz Default (SDH): 64/8 kHz
3
I3
0011
TTL/CMOS
Up to 100 MHz (see Note (i))
Default (SONET): 8 kHz Default (SDH): 8 kHz
4
I4
0100
TTL/CMOS
Up to 100 MHz (see Note (i))
Default (SONET): 8 kHz Default (SDH): 8 kHz
5
I5
0101
LVDS/PECL LVDS Up to 155.52 MHz (see Note (ii))
default
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
6
I6
0110
PECL/LVDS PECL Up to 155.52 MHz (see Note (ii))
default
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
7
I7
0111
TTL/CMOS
Up to 100 MHz (see Note (i))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
8
I8
1000
TTL/CMOS
Up to 100 MHz (see Note (i))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
9
I9
1001
TTL/CMOS
Up to 100 MHz (see Note (i))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
10
I10
1010
TTL/CMOS
Up to 100 MHz (see Note (i))
Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz
11
I11
1011
TTL/CMOS
Up to 100 MHz (see Note (i)) Default (Master) (SONET): 1.544 MHz Default 12/1
(Master) (SDH): 2.048 MHz Default (Slave) 6.48 MHz
(Note (iii))
I12
1100
TTL/CMOS
Up to 100 MHz (see Note (i))
Default (SONET): 1.544 MHz Default (SDH): 2.048 MHz
13
Revision 3.02/November 2005 © Semtech Corp.
Page 11
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