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PDF ACS8526 Data sheet ( Hoja de datos )
| Número de pieza | ACS8526 | |
| Descripción | Line Card Protection Switch | |
| Fabricantes | Semtech Corporation | |
| Logotipo |  |
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ACS8526 LC/P LITE
Line Card Protection Switch for PDH, SONET
or SDH Systems
ADVANCED COMMUNICATIONS
Deswcwrwi.pDattiaoSnheet4U.com
FINAL
Features
DATASHEET
The ACS8526 is a highly integrated single-chip solution
for protection switching between two SECs (SDH/SONET
Equipment Clocks) from Master and Slave SETS clock
cards, for line cards in a PDH, SONET or SDH Network
Element. The ACS8526 has fast activity monitors on the
inputs and will raise a flag on a pin if there is a loss of
activity on the currently selected input. The protection
switching between the input reference clock sources is
controlled by an external pin.
The ACS8526 has two SEC reference clock input ports,
configured for expected frequency by setting hardware
pins or by writing to registers via the serial interface.
The ACS8526 can perform frequency translation,
converting, for example, an 8 kHz SEC input clock from a
backplane into a 155.52 MHz clock for local line cards.
The ACS8526 generates two independent SEC clock
outputs, one on a PECL/LVDS port and one on a
TTL/CMOS port, at spot frequencies configured by
hardware pins, or by writing to registers via the serial
interface. The hardware selectable spot frequencies
range from 1.544 MHz up to 155.52 MHz, with further
options for N x E1/DS1 and 311.04 MHz via register
selection. The ACS8526 also provides an 8 kHz Frame
Sync output and 2 kHz Multi-Frame Sync output, both with
programmable pulse width and polarity.
Advanced configuration possibilities are available via the
serial port (which can be SPI compatible), however the
basic configuration of I/O frequencies and SONET/SDH
selection by hardware make the device suitable for
standalone operation, i.e., no need for a microprocessor.
Block Diagram
Line card protection switch - partners Semtech SETS
devices for Stratum 3E/3/4E/4 PDH, SONET or SDH
applications
High performance DPLL/APLL solution
Output jitter compliant to STM-1
Two independent SEC inputs ports (TTL)
Four independent output ports:
Two clock ports: one PECL/LVDS, one TTL
Two Syncs (TTL): 8 kHz FrSync & 2 KHz MFrSync
TTL I/O ports: spot frequencies 2 kHz to 77.76 MHz
PECL/LVDS port: spot frequencies 2 kHz to 311 MHz
N x E1/DS1 mode
Programmable pulse width and polarity on Syncs
SONET/SDH frequency translation
Digital Holdover mode on input failure
Separate activity monitors and register alarms on
each input.
“Loss of activity” on selected input flagged on
dedicated pin
Source switch under external hardware control
PLL “Locked” and “Acquisition” bandwidth selectable
from 18, 35 or 70 Hz
Configurable via serial interface or hardware pins
Output clock phase continuity to GR-1244-CORE[13]
Single 3.3 V operation, 5 V I/O compatible
IEEE 1149.1 JTAG Boundary Scan is supported
Operating temperature (ambient) of -40 to +85°C
Available in LQFP 64 package
Lead (Pb)-free version available (ACS8526T), RoHS
and WEEE compliant.
Figure 1 Block Diagram of the ACS8526 LC/P LITE
LOS_ALARM
IP_FREQ
SONSDHB
2 x SEC TTL inputs
DPLL1
DPLL2
SEC Inputs: SEC1
Programmable
Frequencies
N x 8 kHz
1.544 MHz
SEC2
2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
SRCSW
38.88 MHz TCK
51.84 MHz
77.76 MHz
TDI
TMS
TRST
TDO
Input
SEC Port
Selector
Digital Feedback
APLL3
E1/DS1
Synthesis
IEEE
1149.1
JTAG
Chip
Clock
Generator
Priority Register Set
Table
MUX
2
MUX
1
APLL2
APLL 1
Output
Port
Frequency
Selection
SPI Compatible
Serial Interface
Port
TCXO or
XO
F8526D_001BLOCKDIA_03
OP_FREQ1
OP_FREQ2
SEC Outputs:
01 (LVDS/PECL)
02 (TTL)
Sync Outputs:
MFrSync 2 kHz (TTL)
FrSync 8 kHz (TTL)
Output Frequencies/MHz
01 Output: 02 Output:
19.44
1.544
25.92
2.048
34.368 (E3) 3.088
38.88
19.44
44.736 (DS3) 25.92
51.84
34.368 (E3)
77.76
38.88
155.52
44.736 (DS3)
51.84
77.76
Revision 4.01/June 2006 © Semtech Corp.
Page 1
www.semtech.com
1 page  
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
Tableww3w.ODathtaeSrhePeitn4Us.co(mcont...)
Pin Number
Symbol
I/O
Type
18
MFrSync
O TTL/CMOS
19, O1POS,
20 O1NEG
O LVDS/PECL
28
IP_FREQ0
I TTLD
29 SEC1
I TTLD
30 SEC2
I TTLD
33
IP_FREQ1
I TTLD
34
IP_FREQ2
I TTLD
35
O2_FREQ0
I TTLD
36
O2_FREQ2
I TTLD
37 TRST
I TTLD
38
O2_FREQ1
I TTLD
41 TMS
I TTLD
42 CLKE
I TTLD
43 SDI
44 CSB
I TTLD
I TTLU
45
O1_FREQ0
I TTLU
46
O1_FREQ1
I TTLU
47 SCLK
I TTLD
48 PORB
I TTLU
49 TCK
50 TDO
I TTLD
O TTL/CMOS
51 TDI
I TTLD
52 SDO
O TTLD
56 O2
O TTL/CMOS
63
O1_FREQ2
I TTLU
64
SONSDHB
I TTLD
Revision 4.01/June 2006 © Semtech Corp.
FINAL
DATASHEET
Description
Output Reference: 2 kHz Multi-Frame Sync output.
Output Reference 1: Differential output., default LVDS.
Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.
Input Reference 1: Primary input.
Input Reference 2: Secondary input.
Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.
Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.
Output O2 Frequency Select: Frequency select for output O2.
Output O2 Frequency Select: Frequency select for output O2.
JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode.
TRST = 0 for normal device operation (JTAG logic transparent). NC if not used.
Output O2 Frequency Select: Frequency select for output O2.
JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK.
NC if not used.
SCLK Edge Select: SCLK active edge select, CLKE = 1, selects falling edge of
SCLK to be active.
Interface Address: SPI compatible Serial Data Input.
Chip Select (Active Low): This pin is asserted Low by the external device
(microprocessor) to enable the Serial interface.
Output O1 Frequency Select: Frequency select for output O1.
Output O1 Frequency Select: Frequency select for output O1.
Serial Data Clock: The Low to High transition on this input latches the data on the
SDI input into the internal registers. The active clock edge (defined by CLKE)
latches the data out of the internal registers onto the SDO output.
Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset
back to default values.
JTAG Clock: Boundary Scan clock input.
JTAG Output: Serial test data output. Updated on falling edge of TCK.
JTAG Input: Serial test data Input. Sampled on rising edge of TCK. NC if not used.
Interface Address: SPI compatible Serial Data Output.
Output Reference: Programmable, default 19.44 MHz.
Output O1 Frequency Select: Frequency select for output O1.
SONET or SDH frequency select: Sets the initial power-up state (or state after a
PORB) of the SONET/SDH frequency selection registers, Reg. 34, Bit 2 and
Reg. 38, Bit 5, Bit 6 and Reg. 64 Bit 4. The register states can be changed after
power-up by software. When set Low, SDH rates are selected (2.048 MHz etc.)
and when set High, SONET rates are selected (1.544 MHz etc.) The register
states can be changed after power-up by software.
Page 5
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5 Page 
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
rangwewowf.DoauttapSuheteftr4eUq.cuoemncies and levels of jitter
performance. However if the device is configured by
hardware alone, then the PLLs are configured as shown in
Table 7 and 8.
divided to 8 kHz and this will ensure synchronization of
frequencies, from 8kHz upwards, within the two DPLLs.
Both of the DPLLs’ outputs can be connected to
Digital Synthesis is used to generate all required
SONET/SDH output frequencies. The digital logic
operates at 204.8 MHz that is multiplied up from the
external 12.800 MHz oscillator module. Hence the best
resolution of the output signals from the DPLLs is one
204.8 MHz cycle or 4.9 ns.
Additional resolution and lower final output jitter is
provided by a de-jittering APLL that reduces the 4.9 ns p-p
jitter from the digital down to 500 ps p-p and 60 ps RMS
as typical final outputs measured broadband (from 10 Hz
to 1 GHz). This arrangement combines the advantages of
the flexibility and repeatability of a DPLL with the low jitter
of an APLL.
multiplying and filtering APLLs. The outputs of these
APLLs are divided making a number of frequencies
simultaneously available for selection at the output clock
ports. The various combinations of DPLL, APLL and divider
configurations allow for generation of a comprehensive
set of frequencies, as listed in Table 9, “Output Frequency
Selection,” on page 19.
A function is provided to synchronize the lower output
frequencies when DPLL1 is locked to a high frequency
reference input. The dividers that generate the 2 kHz and
8 kHz outputs are reset such that the output 2/8 kHz
clocks are lined up with the input 2 kHz.
The DPLLs in the ACS8526 are programmable for
parameters of bandwidth (18, 35 and 70 Hz) and
damping factor (from 1.2 to 20). See Sections “DPLL1
Jitter Transfer Characteristic, (Freq. = 1.544 MHz, Jitter =
0.2 UI p-p, Damping Factor = 5)” on page 14, and
“Damping Factor Programmability” on page 15.
DPLL1 input frequency is programmable with 12 common
SONET/SDH spot frequencies. See
cnfg_nominal_frequency Reg. 3C and Reg. 3D
The DPLL has programmable frequency acceptance and
output range (from 0 to 80 ppm) set by the allowable
offset between the expected input frequency and the
calibrated external frequency, Reg. 41 and Reg. 42).
There is no requirement to understand the loop filter
equations or detailed gain parameters since all high level
factors such as overall bandwidth can be set directly in
registers via the microprocessor interface. No external
critical components are required for either the internal
DPLLs or APLLs, providing another key advantage over
traditional discrete designs.
The PLL configurations required for particular output
frequencies are described in “Output Frequency Selection
by Hardware” on page 17, and “Output Frequency
Selection by Register Programming” on page 17.
An advanced feature of the device is its ability to control
the amount of jitter and wander that is tolerated on the
input. This is achieved by the configuration of the Phase
and Frequency detectors within the DPLLs, which
determines the phase error input to the Digital Loop Filter.
For basic operation, the configuration should not be
changed from the default settings.
PLL Architecture
Figure 4 shows the PLL arrangement in more detail. Each
DPLL comprises a generic Phase and Frequency Detector
(PFD) with a Digital Loop filter, together with Forward,
Feedback, and Low Frequency (LF) (DPLL1 only) Digital
Frequency Synthesis (DFS) blocks. The Forward DFS block
represents a Digital Timed Oscillator (DTO).
DPLL1 always produces an output at 77.76 MHz to feed
the APLL, regardless of the frequency selected at the
output pins or the locking frequency (frequency at the
input of the Phase and Frequency Detector- PFD).
DPLL2 can be operated at a number of frequencies. This
is to enable the generation of extra output frequencies,
which cannot be easily related to 77.76 MHz. If DPLL2 is
enabled, it locks to the 8 kHz from DPLL1. This is because
all of the frequencies of operation of DPLL2 can be
The DPLL architecture for DPLL1 is more complex than
that of DPLL2. See “DPLL Feature Summary” on page 16..
The selected SEC input is always supplied to DPLL1.
DPLL1 may use either digital feedback or analog
feedback (via APLL3).
DPLL2 always takes its feed from DPLL1 and cannot be
used to select a different input to that of DPLL1.
Revision 4.01/June 2006 © Semtech Corp.
Page 11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ACS8526.PDF ] | |
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