ACS8522 Datasheet PDF - Semtech Corporation
| Part Number | ACS8522 | |
| Description | Synchronous Equipment Timing Source | |
| Manufacturers | Semtech Corporation | |
| Logo |  |
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ACS8522 SETS LITE
Synchronous Equipment Timing Source for
Stratum 3/4E/4 and SMC Systems
ADVANCED COMMUNICATIONS
Deswcwrwi.pDattiaoSnheet4U.com
FINAL
Features
DATASHEET
The ACS8522 is a highly integrated, single-chip solution
for the Synchronous Equipment Timing Source (SETS)
function in a SONET or SDH Network Element. The device
generates SONET or SDH Equipment Clocks (SEC) and
Frame Synchronization clocks. The ACS8522 is fully
compliant with the required international specifications
and standards.
The device supports Free-run, Locked and Holdover
modes, with mode selection controlled either
automatically by an internal state machine or forced by
register configuration.
The ACS8522 accepts up to four independent input SEC
reference clock sources from Recovered Line Clock, PDH
network, and Node Synchronization. The ACS8522
generates independent SEC and BITS clocks, an 8 kHz
Frame Synchronization clock and a 2 kHz Multi-Frame
Synchronization clock, both with programmable pulse
width and polarity.
The ACS8522 includes a Serial Port, which can be SPI
compatible, providing access to the configuration and
status registers for device setup.
The ACS8522 supports IEEE 1149.1[5] JTAG boundary
scan.
The User can choose between OCXO or TCXO to define the
Stratum and/or Holdover performance required.
Block Diagram
Suitable for Stratum 3, 4E, 4 and SONET Minimum
Clock (SMC) or SONET/SDH Equipment Clock (SEC)
applications (to Telcordia 1244-CORE[19] Stratum 3
and GR-253[17], and ITU-T G.813[11] Options Ι and ΙΙ
specifications)
Accepts four individual input reference clocks, all with
robust input clock source quality monitoring
Simultaneously generates four output clocks, plus two
Sync pulse outputs
Absolute Holdover accuracy better than 3 x 10-10
(manual), 7.5 x 10-14 (instantaneous); Holdover
stability defined by choice of external XO
Programmable PLL bandwidth, for wander and jitter
tracking/attenuation, 0.1 Hz to 70 Hz in 10 steps
Automatic hit-less source switchover on loss of input
Serial SPI compatible interface
Output phase adjustment in 6 ps steps up to ±200 ns
IEEE 1149.1[5] JTAG Boundary Scan
Available in LQFP 64-pin package
Single 3.3 V operation. 5 V tolerant
Lead (Pb)-free version available (ACS8522T), RoHS
and WEEE compliant.
Figure 1 Block Diagram of the ACS8522 SETS LITE
Inputs: 4 x TTL
Programmable;
2 kHz
4 kHz
N x 8 kHz
1.544/2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
Input
Port
Monitors
and
Selection
Control
4 x SEC
T4 DPLL
Selector
T4 DPLL/Freq. Synthesis
Digital
Optional
Divider, 1/n
n = 1 to 214
PFD
Loop
Filter
DTO
T0 DPLL
Selector
T0 DPLL/Freq. Synthesis
Optional
Divider, 1/n
n = 1 to 214
PFD
Digital
Loop
Filter
DTO
TCK
TDI
TMS
TRST
TDO
IEEE
1149.1
JTAG
Chip
Clock
Generator
Priority Register Set
Table
OCXO or
TCXO
Revision 5/November 2006 © Semtech Corp.
Serial
Port
Page 1
T4 Output
APLL
Frequency
Dividers
T0 Output
APLL
Frequency
Dividers
T0 Feedback
APLL
Output
Ports
O1
to
O4
Output O1: PECL/LVDS
Outputs O2 - 04: TTL
Programmable;
E1/DS1 (2.048/
1.544 MHz)
and frequency
multiples:
1.5 x, 2 x, 3 x
4 x, 6 x, 12 x
16 x and 24 x
E3/DS3
2 kHz
8 kHz
and OC-N* rates
FrSync
&
MFrSync
8 kHz
(FrSync)
2 kHz
(MFrSync)
OC-N* rates =
OC-1 51.84 MHz
OC-3 155.52 MHz
and derivatives:
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
F8522P_001BLOCKDIA_04
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ACS8522 SETS LITE
ADVANCED COMMUNICATIONS
PinwDwwe.DsactarSipheteito4Un.com
Table 1 Power Pins
Pin Number
Symbol
8, 9, VD1+, VD2+,
12 VD3+
22 VDD_DIFF
I/O
P
P
Type
-
-
27 VDD5V
P
-
32, 36,
38, 39,
45, 46,
54
4
14, 57
15, 58
7, 10,
11
31, 40,
53
21
1, 3
VDD1, VDD2,
VDD3, VDD4,
VDD5, VDD6,
VDD7
VA1+
P
P
VA2+, VA3+
P
AGND3, AGND4
DGND1, DGND2,
DGND3
DGND4, DGND5,
DGND6
GND_DIFF
AGND1, AGND2
P
P
P
P
-
-
-
-
-
-
-
-
FINAL
DATASHEET
Description
Supply Voltage: Digital supply to gates in analog section, +3.3 Volts
±10%.
Supply Voltage: Digital supply for differential output pins 19 and 20,
+3.3 Volts ±10%.
VDD5V: Digital supply for +5 Volts tolerance to input pins. Connect to
+5 Volts (±10%) for clamping to +5 Volts. Connect to VDD for clamping
to +3.3 Volts. Leave floating for no clamping. Input pins tolerant up to
+5.5 Volts.
Supply Voltage: Digital supply to logic, +3.3 Volts ±10%.
Supply Voltage: Analog supply to clock multiplying PLL,
+3.3 Volts ±10%.
Supply Voltage: Analog supply to output PLLs APLL2 and APLL1,
+3.3 Volts ±10%.
Supply Ground: Analog ground for output PLLs APLL2 and APLL1.
Supply Ground: Digital ground for components in PLLs.
Supply Ground: Digital ground for logic.
Supply Ground: Digital ground for differential output pins 19 and 20.
Supply Ground: Analog grounds.
Note...I = Input, O = Output, P = Power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor.
Table 2 Internally Connected Pins
Pin Number
Symbol
2, 16, 23, 24,
25, 26, 35,
60, 61, 62,
63
IC1, IC2, IC3, IC4,
IC5, IC6, IC7,
IC8, IC9, IC10,
IC11
I/O
-
Type
-
Description
Internally Connected: Leave to Float.
Table 3 Other Pins
Pin Number
Symbol
5 INTREQ
6 REFCLK
I/O
O
I
Type
TTL/CMOS
TTL
Description
Interrupt Request: Active High/Low software Interrupt output.
Reference Clock: 12.800 MHz (refer to section headed Local Oscillator
Clock).
Revision 5/November 2006 © Semtech Corp.
Page 5
www.semtech.com
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| Information | Total 30 Pages | |
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