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ACS8509 Schematic ( PDF Datasheet ) - Semtech Corporation

Teilenummer ACS8509
Beschreibung Synchronous Equipment Timing Source
Hersteller Semtech Corporation
Logo Semtech Corporation Logo 




Gesamt 30 Seiten
ACS8509 Datasheet, Funktion
ACS8509 SETS
Synchronous Equipment Timing Source for
SONET or SDH Network Elements
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Deswcwrwi.pDattiaoSnheet4U.com
Features
The ACS8509 is a highly integrated, single-chip solution
for the Synchronous Equipment Timing Source (SETS)
function in a SONET or SDH Network Element. The device
generates SONET or SDH Equipment Clocks (SEC) and
Frame Synchronization clocks. The ACS8509 is fully
compliant with the required international specifications
and standards.
‹ Suitable for Stratum 3E*, 3, 4E, 4 and SONET
Minimum Clock (SMC) or SONET/SDH Equipment
Clock (SEC) applications
‹ Meets AT&T, ITU-T, ETSI and Telcordia specifications
‹ Accepts four individual input reference clocks
‹ Generates six output clocks
The device supports Free-run, Locked and Holdover
modes. It also supports all three types of reference clock
source: recovered line clock, PDH network, and node
synchronization. The ACS8509 generates independent
SEC and BITS/SSU clocks, an 8 kHz Frame
Synchronization clock and a 2 kHz Multi-Frame
Synchronization clock.
‹ Supports Free-run, Locked and Holdover modes of
operation
‹ Robust input clock source quality monitoring on all
inputs
‹ Automatic “hit-less” source switchover on loss of input
‹ Phase build-out for output clock phase continuity
during input switchover and mode transitions
Two ACS8509 devices can be used together in a Master/
Slave configuration mode allowing system protection
against a single ACS8509 failure.
A microprocessor port is incorporated, providing access to
the configuration and status registers for device setup
and monitoring.
The ACS8509 includes a choice of edge alignment for
8 kHz input, as well as a low jitter n x E1/DS1 output
mode. The User can choose between OCXO or TCXO to
define the Stratum and/or Holdover performance
required.
Block Diagram
‹ Microprocessor interface - Intel, Motorola, Serial,
Multiplexed, EPROM
‹ Programmable wander and jitter tracking attenuation
0.1 Hz to 20 Hz
‹ Support for Master/Slave device configuration
alignment and hot/standby redundancy
‹ IEEE 1149.1 JTAG Boundary Scan
‹ Single +3.3 V operation, +5 V I/O compatible
‹ Operating temperature (ambient) -40°C to +85°C
‹ Available in 100 pin LQFP package.
‹ Lead (Pb)-free version available (ACS8509T), RoHS
and WEEE compliant.
Note...* Meets holdover requirements, lowest bandwidth 0.1 Hz.
Figure 1 Block Diagram of the ACS8509 SETS
4 x TTL
Programmable;
2 kHz
4 kHz
N x 8 kHz
1.544/2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
Input
Port
Monitors
and
Selection
Control
4 x SEC
T4 DPLL/Freq. Synthesis
TOUT4
Selector
Divider
PFD
Digital
Loop
Filter
DTO
T0 DPLL/Freq. Synthesis
TOUT0
Selecor
Divider
PFD
Digital
Loop
Filter
DTO
6x
Output
Ports
T0 APLL
(output)
Frequency
Dividers
Programmable Outputs:
01 (PECL (default)/LVDS) =
Programmable: 19.44 MHz (default),
51.84 MHz (OC-1), 77.76 MHz and
155.52 MHz (OC-3)
02 (TTL/CMOS) = 6.48 MHz (default)
19.44 MHz and 25.92 MHz,
and E1/DS1 multiples:
1 x, 2 x, 4 x, 8 x (1.544/2.048 MHz)
03 (TTL/CMOS) = 19.44 MHz (fixed)
04 (TTL/CMOS) =
1.544 MHz/2.048 MHz (E1/DS1)
FrSync (TTL/CMOS) =
8 kHz Frame Sync,
Fixed 50:50 MSR
MFrSync (TTL/CMOS) =
2 kHz Multiframe Sync,
Fixed 50:50 MSR
TCK
TDI
TMS
TRST
TDO
IEEE
1149.1
JTAG
Chip
Clock
Generator
Priority Register Set
Table
Microprocessor
Port
F85509 001BLOCKDIA 01
OCXO or
TCXO
Revision 2.00/January 2006 © Semtech Corp.
Page 1
www.semtech.com






ACS8509 Datasheet, Funktion
ACS8509 SETS
ADVANCED COMMUNICATIONS
Tableww3w.ODathtaeSrhePeitn4Us.co(mcont...)
Pin Number
Symbol
I/O
Type
8
INTREQ
O TTL/CMOS
9 TCK
I TTLD
10
21
23
30
31
36,
37
45
48
51
54
56
58 - 60
63 - 69
70
71
72
73
REFCLK
TDO
I
O
TDI I
FrSync
MFrSync
O1POS, O1NEG
O
O
O
SYNC2K
I
SEC1
I
SEC2
I
SEC3
I
SEC4
UPSEL(2:0)
A(6:0)
CSB
WRB
RDB
ALE
I
I
I
I
I
I
I
TTL
TTL/CMOS
TTLU
TTL/CMOS
TTL/CMOS
PECL/LVDS
TTLD
TTLD
TTLD
TTLD
TTLD
TTLD
TTLD
TTLU
TTLU
TTLU
TTLD
74 PORB
I TTLU
FINAL
DATASHEET
Description
Interrupt Request: Active High software Interrupt output.
JTAG Clock: Boundary Scan clock input. If not used connect to GND or leave
floating. This pin may require a capacitor placed between the pin and the
nearest GND, to reduce noise pickup. A value of 10 pF should be adequate,
but the value is dependent on PCB layout.
Reference Clock: 12.800 MHz (refer to “Local Oscillator Clock” on page 8).
JTAG Output: Serial test data output. Updated on falling edge of TCK. If not
used leave floating.
JTAG Input: Serial test data Input. Sampled on rising edge of TCK. If not
used connect to VDD or leave floating.
Output Reference: 8 kHz Frame Sync output (square wave).
Output Reference: 2 kHz Multi-Frame Sync output (square wave).
Output Reference O1: Programmable, default 19.44 MHz. Also 51.84 MHz,
77.76 MHz, 155.52 MHz. MHz, default type PECL.
Synchronize 2 kHz: Connect to 2 kHz Multi-Frame Sync output of partner
ACS8509 in redundancy system.
Input Reference SEC1: Programmable, default 19.44 MHz
(Default Priority 7).
Input Reference SEC2 : Programmable, default 19.44 MHz
(Default Priority 8).
Input Reference SEC3: Programmable, default (Master mode)
1.544/2.048 MHz, default (Slave mode) 6.48 MHz.
(Default Priority 11).
Input Reference SEC4 (Priority 13): Programmable, default
1.544/2.048 MHz (Default Priority 13).
Microprocessor Select: Configures the interface for a particular
microprocessor type at reset.
Microprocessor Interface Address: Address bus for the microprocessor
interface registers. A(0) is SDI in Serial mode - output in EPROM mode only.
Chip Select (Active Low): This pin is asserted Low by the microprocessor to
enable the microprocessor interface - output in EPROM mode only.
Write (Active Low): This pin is asserted Low by the microprocessor to
initiate a write cycle. In Motorola mode, WRB = 1 for Read.
Read (Active Low): This pin is asserted Low by the microprocessor to
initiate a read cycle.
Address Latch Enable: This pin becomes the address latch enable from the
microprocessor. When this pin transitions from High to Low, the address
bus inputs are latched into the internal registers. ALE = SCLK in Serial
mode.
Power-On Reset: Master reset. If PORB is forced Low, all internal states are
reset back to default values.
Revision 2.00/January 2006 © Semtech Corp.
Page 6
www.semtech.com

6 Page









ACS8509 pdf, datenblatt
ADVANCED COMMUNICATIONS
FINAL
Figurwew3w.DaMtaiSnhimeeut4mU.cIonmput Jitter Tolerance (OC-3/STM-1)
ACS8509 SETS
DATASHEET
A0
A1
A2
A3
A4
Jitter and Wander Frequency (log scale)
f0
f1 f2
f3 f4
Note...For inputs supporting G.783[9] compliant sources.)
f5 f6
f7 f8
f9
F8530_003MINIPJITTOLOC3STM1_02
Table 8 Amplitude and Frequency Values for Jitter Tolerance (OC-3/STM-1)
STM
level
STM-1
Peak to peak amplitude (unit
Interval)
Frequency (Hz)
A0 A1 A2 A3 A4 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9
2800 311 39 1.5 0.15 12 u 178 u 1.6 m 15.6 m 0.125 19.3 500 6.5 k 65 k 1.3m
Frame Sync and Multi-Frame Sync Clocks (Part of
TOUT0)
Frame Sync (8 kHz) and Multi-Frame Sync (2 kHz) clocks
are provided on outputs “FrSync” and “MFrSync”. The
FrSync and MFrSync clocks have a 50:50 mark space
ratio. These are driven from the TOUT0 clock. They are
synchronized with their counterparts in a second
ACS8509 device (if used), using the technique described
later.
Output Clock Ports
The device supports a set of main output clocks, TOUT0
and TOUT4, and a pair of secondary output clocks, “Frame
Sync” and “Multi-Frame Sync”. The two main output
clocks, TOUT0 and TOUT4, are independent of each other
and are individually selectable. The two secondary output
clocks, Frame Sync and Multi-Frame Sync, are derived
from TOUT0. The frequencies of the output clocks are
selectable from a range of pre-defined spot frequencies
and a variety of output technologies are supported, as
defined in Table 10.
Low-speed Output Clock (TOUT4)
The TOUT4 clock is supplied on output port O4. This port
will provide a TTL/CMOS signal at either 1.544 MHz or
2.048 MHz, depending on the setting of the SONSDHB
pin.
High-speed Output Clock (Part of TOUT0)
The TOUT0 port has multiple outputs. Output O1 is
differential and can support clocks up to 155.52 MHz.
Output O2 is a TTL/CMOS output with a choice of 11
different frequencies up to 51.84 MHz. Output O3 is a
TTL/CMOS output with fixed frequency of 19.44 MHz.
Each output is individually configured to operate at the
frequencies shown in Table 10 (configuration must be
consistent between ACS8509 devices for protection-
switching to be effective - output clocks will be phase-
aligned between devices). Using the
cnfg_differential_outputs register, output O1 can be
made to be LVDS or PECL compatible.
Revision 2.00/January 2006 © Semtech Corp.
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