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DAC2904 Schematic ( PDF Datasheet ) - Burr-Brown

Teilenummer DAC2904
Beschreibung 125MSPS DIGITAL-TO-ANALOG CONVERTER
Hersteller Burr-Brown
Logo Burr-Brown Logo 




Gesamt 19 Seiten
DAC2904 Datasheet, Funktion
DAC2904
DAC2904
SBAS198B – NOVEMBER 2003
Dual, 14-Bit, 125MSPS
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q 125MSPS UPDATE RATE
q SINGLE SUPPLY: +3.3V or +5V
www.DataSheet4U.cqomHIGH SFDR: 78dB at fOUT = 10MHz
q LOW GLITCH: 2pVs
q LOW POWER: 310mW
q INTERNAL REFERENCE
q POWER-DOWN MODE: 23mW
DESCRIPTION
The DAC2904 is a monolithic, 14-bit, dual-channel,
high-speed Digital-to-Analog Converter (DAC), and is opti-
mized to provide high dynamic performance while dissipating
only 310mW.
Operating with high update rates of up to 125MSPS, the
DAC2904 offers exceptional dynamic performance, and
enables the generation of very-high output frequencies suit-
able for “Direct IF” applications. The DAC2904 has been
optimized for communications applications in which sepa-
rate I and Q data are processed while maintaining tight-gain
and offset matching.
Each DAC has a high-impedance differential-current output,
suitable for single-ended or differential analog-output con-
figurations.
APPLICATIONS
q COMMUNICATIONS:
Base Stations, WLL, WLAN
Baseband I/Q Modulation
q MEDICAL/TEST INSTRUMENTATION
q ARBITRARY WAVEFORM GENERATORS (ARB)
q DIRECT DIGITAL SYNTHESIS (DDS)
The DAC2904 combines high dynamic performance with a
high update rate to create a cost-effective solution for a wide
variety of waveform-synthesis applications:
• Pin compatibility between family members provides 10-bit
(DAC2900), 12-bit (DAC2902), and 14-bit (DAC2904)
resolution.
• Pin compatible to the AD9767 dual DAC.
• Gain matching is typically 0.5% of full-scale, and offset
matching is specified at 0.02% max.
• The DAC2904 utilizes an advanced CMOS process; the
segmented architecture minimizes output-glitch energy,
and maximizes the dynamic performance.
• All digital inputs are +3.3V and +5V logic compatible. The
DAC2904 has an internal reference circuit, and allows use
in a multiplying configuration.
• The DAC2904 is available in a TQFP-48 package, and is
specified over the extended industrial temperature range of
–40°C to +85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright © 2002-2003, Texas Instruments
Incorporated






DAC2904 Datasheet, Funktion
TYPICAL CHARACTERISTICS
TA = 25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50ý double terminated load, SFDR up to Nyquist, unless otherwise noted.
TYPICAL DNL
4
3
2
1
0
–1
–2
–3
www.DataSheet4U4 .com
0 2k 4k 6k 8k 10k 12k 14k 16k
Code
6
5
4
3
2
1
0
–1
–2
–3
–4
0
TYPICAL INL
2k 4k 6k 8k 10k 12k 14k 16k
Code
90
85
80
75
70
65
60
0
SFDR vs fOUT AT 26MSPS
–6dBFS
0dBFS
–12dBFS
2 4 6 8 10 12
fOUT (MHz)
90
85
80
75
70
65
60
0
SFDR vs fOUT AT 52MSPS
–6dBFS 0dBFS
–12dBFS
5 10 15 20 25
fOUT (MHz)
85
80
75
70
65
60
55
0
SFDR vs fOUT AT 78MSPS
0dBFS
–6dBFS
–12dBFS
5 10 15 20 25
fOUT (MHz)
30 35
SFDR vs fOUT AT 100MSPS
85
80
–6dBFS
75
70
–12dBFS
65
60
0dBFS
55
50
0
5 10 15 20 25 30 35 40 45
fOUT (MHz)
6 DAC2904
SBAS198B

6 Page









DAC2904 pdf, datenblatt
The DC gain for this circuit is equal to feedback resistor RF.
At high frequencies, the DAC output impedance (CD1, CD2)
will produce a zero in the noise gain for the OPA2680 that
may cause peaking in the closed-loop frequency response.
CF is added across RF to compensate for this noise gain
peaking. To achieve a flat transimpedance frequency re-
sponse, the pole in each feedback network should be set to:
IOUTFS = 20mA
IOUT
DAC2904
IOUT
50
25
VOUT = 0V to +0.5V
50
(8)
with GBP = Gain Bandwidth Product of OPA
which will give a corner frequency f-3dB of approximately:
www.DataSheet4U.com
(9)
The full-scale output voltage is simply defined by the prod-
uct of IOUTFS • RF, and has a negative unipolar excursion. To
improve on the ac performance of this circuit, adjustment of
RF and/or IOUTFS should be considered. Further extensions of
this application example may include adding a differential
filter at the OPA2680’s output followed by a transformer, in
order to convert to a single-ended signal.
SINGLE-ENDED CONFIGURATION
Using a single load resistor connected to one of the DAC
outputs, a simple current-to-voltage conversion can be ac-
complished. The circuit in Figure 6 shows a 50resistor
connected to IOUT, providing the termination of the further
connected 50cable. Therefore, with a nominal output
current of 20mA, the DAC produces a total signal swing of
0V to 0.5V into the 25load.
FIGURE 6. Driving a Doubly Terminated 50Cable Directly.
Different load resistor values may be selected as long as the
output compliance range is not exceeded. Additionally, the
output current, IOUTFS, and the load resistor, may be mutu-
ally adjusted to provide the desired output signal swing and
performance.
INTERFACING ANALOG
QUADRATURE MODULATORS
One of the main applications for the dual-channel DAC is
baseband I- and Q-channel transmission for digital commu-
nications. In this application, the DAC is followed by an
analog quadrature modulator, modulating an IF carrier with
the baseband data, as shown in Figure 7. Often, the input
stages of these quadrate modulators consist of npn-type
transistors that require a DC bias (base) voltage of > 0.8V.
The wide output compliance range (–10V to +1.25V) allows
for a direct DC–coupling between the DAC2902 and the
quadrature modulator.
Figure 8 shows an example of a DC-coupled interface with
DC level-shifting, using a precision resistor network. An ac-
coupled interface, see Figure 9, has the advantage that the
common-mode levels at the input of the modulator can be set
independently of those at the output of the DAC. Further-
more, no voltage loss is obtained in this setup.
VOUT ~ 0Vp to 1.20Vp
VIN ~ 0.6Vp to 1.8Vp
IIN
DAC2904
IOUT1
IIN
IOUT1
IOUT2
Signal
Conditioning
IREF
QIN
IOUT2
QREF
Quadrature Modulator
RF
IREF
FIGURE 7. Generic Interface to a Quadrature Modulator. Signal Conditioning (Level-Shifting) May Be Required to Ensure
Correct DC Common-Mode Levels At the Input of the Quadrature Modulator.
12 DAC2904
SBAS198B

12 Page





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