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PDF AD5763 Data sheet ( Hoja de datos )
| Número de pieza | AD5763 | |
| Descripción | DAC | |
| Fabricantes | Analog Devices | |
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Data Sheet
Complete Dual, 16-Bit High Accuracy,
Serial Input, ±5 V DAC
AD5763
FEATURES
Complete dual, 16-bit DAC
Programmable output range
±4.096 V, ±4.201 V, or ±4.311 V
±1 LSB maximum INL error, ±1 LSB maximum DNL error
Low noise: 70 nV/√Hz
Settling time: 10 μs maximum
Integrated reference buffers
On-chip die temperature sensor
Output control during power-up/brownout
Programmable short-circuit protection
Simultaneous updating via LDAC
Asynchronous clear to zero code
Digital offset and gain adjust
Logic output control pins
DSP-/microcontroller-compatible serial interface
Temperature range: −40°C to +105°C
iCMOS® process technology1
APPLICATIONS
Industrial automation
Open-loop/closed-loop servo control
Process control
Data acquisition systems
Automatic test equipment
Automotive test and measurement
High accuracy instrumentation
GENERAL DESCRIPTION
The AD5763 is a dual, 16-bit, serial input, bipolar voltage
output digital-to-analog converter (DAC) that operates from
supply voltages of ±4.75 V up to ±5.25 V. The nominal full-
scale output range is ±4.096 V. The AD5763 provides integrated
output amplifiers, reference buffers, and proprietary power-up/
power-down control circuitry. The part also features a digital
I/O port, which is programmed via the serial interface. The part
incorporates digital offset and gain adjust registers per channel.
The AD5763 is a high performance converter that offers guar-
anteed monotonicity, integral nonlinearity (INL) of ±1 LSB,
low noise, and 10 μs settling time. During power-up (when the
supply voltages are changing), the outputs are clamped to 0 V
via a low impedance path.
The AD5763 uses a serial interface that operates at clock rates of
up to 30 MHz and is compatible with DSP and microcontroller
interface standards. Double buffering allows the simultaneous
updating of all DACs. The input coding is programmable to either
twos complement or offset binary formats. The asynchronous
clear function clears all DAC registers to either bipolar zero or
zero scale depending on the coding used. The AD5763 is ideal
for both closed-loop servo control and open-loop control appli-
cations. The AD5763 is available in a 32-lead TQFP, and offers
guaranteed specifications over the −40°C to +105°C industrial
temperature range. Figure 1 contains a functional block diagram
of the AD5763.
Table 1. Related Devices
Part No.
Description
AD5764
Complete quad, 16-bit, high accuracy, serial
input, ±10 V output DAC
AD5765
Complete quad, 16-bit, high accuracy, serial
input, ±5 V DAC
1 iCMOS, Reg. U.S. Patent and Trademark Office.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved.
1 page  
AD5763
Data Sheet
SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, AVSS = −5.25 V to −4.75 V, AGNDx = DGND = REFGND = PGND = 0 V, REFA = REFB = 2.048 V,
DVCC = 2.7 V to 5.25 V, RLOAD = 5 kΩ, CLOAD = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
ACCURACY
Resolution
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Bipolar Zero Error
Bipolar Zero Temperature
Coefficient (TC)1
Zero-Scale Error
Zero-Scale Temperature Coefficient
(TC)1
Gain Error
Gain Temperature Coefficient (TC)1
DC Crosstalk1
REFERENCE INPUT1
Reference Input Voltage
DC Input Impedance
Input Current
Reference Range
OUTPUT CHARACTERISTICS1
Output Voltage Range2
Output Voltage Drift vs. Time
Short-Circuit Current
Load Current
Capacitive Load Stability
RLOAD = ∞
RLOAD = 10 kΩ
DC Output Impedance
DIGITAL INPUTS1
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current
Pin Capacitance
DIGITAL OUTPUTS (D0, D1, SDO)1
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
High Impedance Leakage Current
High Impedance Output
Capacitance
Min
Typ Max
Unit
16
−1
−1
−2
−3
−2
−3.5
−0.03
−0.04
+1
+1
+2
+3
±1
+2
+3.5
±1
+0.03
+0.04
±1
0.5
Bits
LSB
LSB
mV
mV
ppm FSR/°C
mV
mV
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
LSB
2.048
V nominal
1 MΩ
0.03 10
μA
1 2.1 V
−4.31158
−4.20103
−4.096
−4.42105
−1
±32
±37
10
+4.31158
+4.20103
+4.096
+4.42105
+1
V
V
V
V
ppm FSR/500 hrs
ppm FSR/1000 hrs
mA
mA
200
1000
0.3
pF
pF
Ω
2V
0.8 V
−1 +1 μA
10 pF
DVCC − 1
DVCC − 0.5
±1
5
0.4
0.4
V
V
V
V
μA
pF
Test Conditions/Comments
Outputs unloaded
Guaranteed monotonic
At 25°C
At 25°C
At 25°C, coarse gain register = 0
Coarse gain register = 0
±1% for specified performance
Typically 100 MΩ
Coarse gain register = 2
Coarse gain register = 1
Coarse gain register = 0
REFA = REFB = 2.1 V, coarse gain register = 2
RISCC = 6 kΩ, see Figure 23
For specified performance
JEDEC compliant
Per pin
Per pin
DVCC = 5 V ± 5%, sinking 200 μA
DVCC = 5 V ± 5%, sourcing 200 μA
DVCC = 2.7 V to 3.6 V, sinking 200 μA
DVCC = 2.7 V to 3.6 V, sourcing 200 μA
SDO only
SDO only
Rev. C | Page 4 of 29
5 Page 
AD5763
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
SYNC
SCLK
SDIN
SDO
CLR
LDAC
D0
D1
32
1
8
9
PIN 1
INDICATOR
AD5763
TOP VIEW
(Not to scale)
25
24
17
16
NC
NC
VOUTA
AGNDA
AGNDB
VOUTB
NC
NC
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
1 SYNC
2 SCLK
3 SDIN
4 SDO
51 CLR
6 LDAC
7, 8 D0, D1
9 RSTOUT
10 RSTIN
11
12
13, 31
14
15, 30
16
DGND
DVCC
AVDD
PGND
AVSS
ISCC
17, 18, 23, 24, 27 NC
19 VOUTB
20 AGNDB
21 AGNDA
NC = NO CONNECT
Figure 6. Pin Configuration
Description
Active Low Input. This pin is the frame synchronization signal for the serial interface. While SYNC is
low, data is transferred in on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin
operates at clock speeds up to 30 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode.
Negative Edge Triggered Input. Asserting this pin sets the DAC registers to 0x0000.1
Load DAC. Logic input. This pin is used to update the DAC registers and consequently the analog
outputs. When LDAC is tied permanently low, the addressed DAC register is updated on the rising
edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated but the
output update is held off until the falling edge of LDAC. In this mode, all analog outputs can be
updated simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected.
D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are confi-
gurable and readable over the serial interface. When configured as inputs, these pins have weak
internal pull-ups to DVCC. When programmed as outputs, D0 and D1 are referenced by DVCC and DGND.
Reset Logic Output. This pin is the output from the on-chip voltage monitor used in the reset
circuit. If desired, it can be used to control other system components.
Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to
this input clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1.
Register values remain unchanged.
Digital Ground Pin.
Digital Supply Pin. The voltage ranges from 2.7 V to 5.25 V.
Positive Analog Supply Pins. The voltage ranges from 4.75 V to 5.25 V.
Ground Reference Point for Analog Circuitry.
Negative Analog Supply Pins. The voltage ranges from –5.25 V to –4.75 V.
This pin is used in association with an optional external resistor connected to AGND and programs
the short-circuit current of the output amplifiers. See the Design Features section for further details.
No Connect.
Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±4.096 V. The
output amplifier is capable of directly driving a 5 kΩ, 200 pF load.
Ground Reference Pin for the DAC B Output Amplifier.
Ground Reference Pin for the DAC A Output Amplifier.
Rev. C | Page 10 of 29
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AD5763.PDF ] | |
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