PDF ADS5273 Data sheet ( Hoja de datos )

Número de pieza	ADS5273
Descripción	70MSPS ADC
Fabricantes	Burr-Brown Corporation
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No Preview Available ! ADS5273 SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 8-Channel, 12-Bit, 70MSPS ADC with Serialized LVDS Interface FEATURES D Maximum Sample Rate: 70MSPS D 12-Bit Resolution www.DataSheet4UD.comNo Missing Codes D Power Dissipation: 1.1W D CMOS Technology D Simultaneous Sample-and-Hold D 70.5dB SNR at 10MHz IF D Serialized LVDS Outputs Meet or Exceed the Requirements of ANSI TIA/EIA-644-A Standard D Internal and External References D 3.3V Digital/Analog Supply D TQFP-80 PowerPAD Package APPLICATIONS D Portable Ultrasound Systems D Tape Drives D Test Equipment DESCRIPTION The ADS5273 is a high-performance, 70MSPS, 8-channel parallel analog-to-digital converter (ADC). An internal reference is provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS outputs reduce the number of interface lines and package size. In LVDS (low-voltage differential signaling), an integrated phase lock loop multiplies the incoming ADC sampling clock by a factor of 6. This high-frequency LVDS clock is used in the data serialization and transmission process and is converted to an LVDS signal for transmission in parallel with the data. Providing this additional LVDS clock allows for easy delay matching. The word output of each internal ADC is serialized and transmitted either MSB or LSB first. The bit following the rising edge of the ADC clock output is the first bit of the word. The ADS5273 provides an internal reference, or can optionally be driven with an external reference. Best performance can be achieved through the internal reference mode. The device is available in a PowerPAD TQFP-80 package and is specified over a −40°C to +85°C operating range. 6X ADCLK ADCLK PLL 1X ADCLK IN1P IN1N S/H IN2P IN2N S/H IN3P IN3N S/H IN4P IN4N S/H IN5P IN5N S/H IN6P IN6N S/H IN7P IN7N S/H IN8P IN8N S/H 12−Bit ADC 12−Bit ADC 12−Bit ADC 12−Bit ADC 12−Bit ADC 12−Bit ADC 12−Bit ADC 12−Bit ADC Serializer Serializer Serializer Serializer Serializer Serializer Serializer Serializer Reference Registers Control INT/EXT LCLKP LCLKN ADCLKP ADCLKN OUT1P OUT1N OUT2P OUT2N OUT3P OUT3N OUT4P OUT4N OUT5P OUT5N OUT6P OUT6N OUT7P OUT7N OUT8P OUT8N Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. www.ti.com Copyright  2004, Texas Instruments Incorporated 1 page ADS5273 www.ti.com SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 SWITCHING CHARACTERISTICS TMIN = −40°C, TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, −0.5dBFS, internal voltage reference, and 2VPP differential input, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS SWITCHING SPECIFICATIONS tSAMPLE tD(A) Aperture Delay Aperture Jitter (uncertainty) 14.3 120 1 50 ns ps ps tD(pipeline) Latency tPROP Propagation Delay 6.5 cycles 5 ns SERIAL INTERFACE TIMING www.DataSheet4UD.caotamis shifted in MSB first. Outputs change on next rising clock edge after CS goes high. ADCLK CS SCLK Start Sequence t1 t2 t3 Data latched on each rising edge of SCLK. SDATA MSB D6 D5 D4 D3 D2 D1 D0 t4 t5 PARAMETER t1 t2 t3 t4 t5 DESCRIPTION Serial CLK Period Serial CLK High Time Serial CLK Low Time Data Setup Time Data Hold Time MIN TYP MAX UNIT 50 ns 13 ns 13 ns 5 ns 5 ns 5 5 Page ADS5273 www.ti.com THEORY OF OPERATION OVERVIEW The ADS5273 is an 8-channel, high-speed, CMOS ADC, consisting of a high-performance sample-and-hold circuit at the input, followed by a 12-bit ADC. The 12 bits given out by each channel are serialized and sent out on a single pair of pins in LVDS format. All eight channels of the ADS5273 operate from a single clock referred to as ADCLK. The sampling clock for each of the eight channels is generated from the input clock using a carefully matched clock buffer tree. The 12X clock required for the serializer is generated internally from ADCLK using a phase lock loop (PLL). A 6X www.DataSheet4Ua.cnodma 1X clock are also output in LVDS format along with the data to enable easy data capture. The ADS5273 operates from an internally generated reference voltage that is trimmed to ensure matching across multiple devices on a board. This feature eliminates the need for external routing of reference lines and also improves matching of the gain across devices. The nominal values of REFP and REFN are 2V and 1V, respectively. These values imply that a differential input of −1V corresponds to the zero code of the ADC, and a differential input of +1V corresponds to the full-scale code (4095 LSB). VCM (common-mode voltage of REFP and REFN) is also made available externally through a pin, and is nominally 1.5V. The ADC employs a pipelined converter architecture consisting of a combination of multi-bit and single-bit internal stages. Each stage feeds its data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at the 12-bit level. The pipeline architecture results in a data latency of 6.5 clock cycles. The output of the ADC goes to a serializer that operates from a 12X clock generated by the PLL. The 12 data bits from each channel are serialized and sent LSB first. In addition to serializing the data, the serializer also generates a 1X clock and a 6X clock. These clocks are generated in the same way the serialized data is generated, so these clocks maintain perfect synchroniza- tion with the data. The data and clock outputs of the serializer are buffered externally using LVDS buffers. Using LVDS buffers to transmit data externally has multiple advantages, such as a reduced number of output pins (saving routing space on the board), reduced power consumption, and reduced effects of digital noise coupling to the analog circuit inside the ADS5273. The ADS5273 operates from two sets of supplies and grounds. The analog supply/ground set is denoted as AVDD/AVSS, while the digital set is denoted by LVDD/LVSS. SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004 DRIVING THE ANALOG INPUTS The analog input biasing is shown in Figure 1. The recommended method to drive the inputs is through AC coupling. AC coupling removes the worry of setting the common-mode of the driving circuit, since the inputs are biased internally using two 600Ω resistors. The sampling capacitor used to sample the inputs is 4pF. The choice of the external AC coupling capacitor is dictated by the attenuation at the lowest desired input frequency of operation factor. The attenuation resulting from using a 10nF AC coupling capacitor is 0.04%. IN+ 600Ω 600Ω IN− VCM CM Buffer 1 CM Buffer 2 ADS5273 Input Circuitry Internal Voltage Reference Figure 1. Analog Input Bias Circuitry If the input is DC coupled, then the output common-mode voltage of the circuit driving the ADS5273 should match the VCM (which is provided as an output pin) to within ±50mV. It is recommended that the output common-mode of the driving circuit be derived from VCM provided by the device. INPUT OVER-VOLTAGE RECOVERY The differential full-scale input peak-to-peak supported by the ADS5273 is 2V. For a nominal value of VCM (1.5V), INP and INN can swing from 1V to 2V. The ADS5273 is specially designed to handle an over-voltage differential peak-to-peak voltage of 4V (2.5V and 0.5V swings on INP and INN). If the input common-mode is not considerably off from VCM during overload (less than 300mV), recovery from an over-voltage input condition is expected to be within 4 clock cycles. All of the amplifiers in the SHA and ADC are especially designed for excellent recovery from an overload signal. 11 11 Page

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