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ADS5272 Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS5272
Beschreibung 65MSPS ADC
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 16 Seiten
ADS5272 Datasheet, Funktion
ADS5272
8-Channel, 12-Bit, 65MSPS ADC
with Serial LVDS Interface
SBAS324 − JUNE 2004
FEATURES
D Maximum Sample Rate: 65MSPS
D 12-Bit Resolution
D No Missing Codes
www.DataSheet4UD.comPower Dissipation: 996mW
D CMOS Technology
D Simultaneous Sample-and-Hold
D 70.5dB SNR at 10MHz IF
D Internal and External References
D 3.3V Digital/Analog Supply
D Serialized LVDS Outputs
D Integrated Frame and Synch Patterns
D MSB and LSB First Modes
D Option to Double LVDS Clock Output Currents
D Pin- and Format-Compatible Family
D TQFP-80 PowerPADPackage
APPLICATIONS
D Portable Ultrasound Systems
D Tape Drives
D Test Equipment
D Optical Networking
DESCRIPTION
or LSB first. The bit coinciding with the rising edge of the 1x
clock output is the first bit of the word. Data is to be latched by
the receiver on both the rising and falling edges of the 6x clock.
The ADS5272 provides internal references, or can optionally
be driven with external references. Best performance can be
achieved through the internal reference mode.
The device is available in a TQFP-80 PowerPAD package and
is specified over a −40°C to +85°C operating range.
6X ADCLK
ADCLK
IN1P
IN1N
S/H
IN2P
IN2N
S/H
IN3P
IN3N
S/H
IN4P
IN4N
S/H
IN5P
IN5N
S/H
PLL
1X ADCLK
12−Bit
ADC
12−Bit
ADC
12−Bit
ADC
12−Bit
ADC
12−Bit
ADC
Serializer
Serializer
Serializer
Serializer
Serializer
LCLKP
LCLKN
ADCLKP
ADCLKN
OUT1P
OUT1N
OUT2P
OUT2N
OUT3P
OUT3N
OUT4P
OUT4N
OUT5P
OUT5N
The ADS5272 is a high-performance, 65MSPS, 8-channel,
parallel analog-to-digital converter (ADC). Internal references
are provided, simplifying system design requirements. Low
power consumption allows for the highest of system
integration densities. Serial LVDS (low-voltage differential
signaling) outputs reduce the number of interface lines and
package size.
An integrated phase lock loop multiplies the incoming ADC
sampling clock by a factor of 12. This 12x clock is used in the
process of serializing the data output from each channel. The
12x clock is also used to generate a 1x and a 6x clock, both
of which are transmitted as LVDS clock outputs. The 6x clock
is denoted by the differential pair LCLKP and LCLKN, while the
1x clock is denoted by ADCLKP and ADCLKN. The word
output of each ADC channel can be transmitted either as MSB
IN6P
IN6N
S/H
IN7P
IN7N
S/H
IN8P
IN8N
S/H
12−Bit
ADC
12−Bit
ADC
12−Bit
ADC
Serializer
Serializer
Serializer
Reference
Registers
Control
INT/EXT
OUT6P
OUT6N
OUT7P
OUT7N
OUT8P
OUT8N
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative or design
phase of development. Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or discontinue these
products without notice.
www.ti.com
Copyright 2004, Texas Instruments Incorporated






ADS5272 Datasheet, Funktion
ADS5272
SBAS324 − JUNE 2004
SERIAL INTERFACE TIMING
ADDRESS
DATA
D7 D6 D5 D4 D3 D2 D1
0000
00
01
10
11
0
0
1
www.DataSheet04U.com0 0 1
1
D3 D2 D1
0XX
00X
01X
0010
D3 D2 D1
XXX
0011
D3 D2 D1
XXX
D3 D2 D1
0 1 0 0 MSB X X
0 1 0 1XXX
0 1 1 0XXX
DESCRIPTION
D0
0. LVDS BUFFERS
Normal ADC Output
Deskew Pattern
Sync Pattern
Custom Pattern
0 Output Current in LVDS = 3.5mA
1 Output Current in LVDS = 2.5mA
0 Output Current in LVDS = 4.5mA
1 Output Current in LVDS = 6.0mA
1. LSB/MSB MODE
D0 Default LVDS Clock Output Current
1 2X LVDS Clock Output Current
X LSB Mode
X MSB Mode
2. POWER-DOWN ADC CHANNELS
D0
X
Power-Down Channels 1 to 4; D3 is
for Channel 4 and D0 for Channel 1
3. POWER-DOWN ADC CHANNELS
D0
X
Power-Down Channels 5 to 8; D3 is
for Channel 8 and D0 for Channel 5
CUSTOM PATTERN (registers 4-6)
D0
X
X Bits for Custom Pattern
LSB
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REMARKS
Patterns Get Reversed in MSB First
Mode of LVDS
Example: 1010 Powers Down
Channels 4 and 2 and Keeps
Channels 1 and 3 Alive
TEST PATTERNS(1)
Deskew
101010101010
Sync
000000111111
Custom
Any 12-bit pattern that is defined in the custom pattern registers 4 to 6. The output comes out in the following order:
D0(4) D1(4) D2(4) D3(4) D0(5) D1(5) D2(5) D3(5) D0(6) D1(6) D2(6) D3(6)
where, for example, D0(4) refers to the D0 bit of register 4, etc.
(1) Default is LSB first. If MSB is selected the above patterns will be reversed.
6

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ADS5272 pdf, datenblatt
ADS5272
SBAS324 − JUNE 2004
clock paths for all the channels are matched from the
source point all the way to the sample-and-hold. This
ensures that the performance and timing for all the
channels are identical. The use of the clock tree for
matching introduces an aperture delay, which is defined as
the delay between the rising edge of ADCLK and the actual
instant of sampling. The aperture delays for all the
channels are matched, and vary between 2.5ns to 4.5ns
across devices. Another critical spec is the aperture jitter
that is defined as the uncertainty of the sampling instant.
The gates in the clock path are designed so as to give an
rms jitter of about 1ps.
The input ADCLK should ideally have a 50% duty cycle.
www.DataShHeeotw4Ue.vceomr, while routing ADCLK to different components on
board, the duty cycle of the ADCLK reaching the ADS5272
could deviate from 50%. A smaller (or larger) duty cycle
eats into the time available for sample or hold phases of
each circuit, and is therefore not optimal. For this reason,
the internal PLL is used to generate an internal clock that
has 50% duty cycle.
The use of the PLL automatically dictates the lower
frequency of operation to be about 20MHz.
LVDS BUFFERS
The LVDS buffer has two current sources, as shown in
Figure 4. OUTP and OUTN are loaded externally by a
resistive load that is ideally about 100. Depending on the
data being 0 or 1, the currents are directed in one or the
other direction through the resistor. The LVDS buffer has
four current settings. The default current setting is 3.5mA,
and gives a differential drop of about ±350mV across the
100resistor.
High
OUTP
External
Termination
Resistor
Low
OUTN
Low High
Figure 4. LVDS Buffer
The LVDS buffer gets data from a serializer that takes the
output data from each channel and serializes it into a
single data stream. For a clock frequency of 40MHz, the
12
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data rate output by the serializer is 480 MBPS. The data
comes out LSB first, with a register programmability to
revert to MSB first. The serializer also gives out a 1X clock
and a 6X clock. The 6X clock (denoted as LCLKP/ LCLKN)
is meant to synchronize the capture of the LVDS data. The
deskew mode can be enabled as well, using a register
setting. This mode gives out a data stream of alternate 0s
and 1s and can be used determine the relative delay
between the 6X clock and the output data for optimum
capture. A 1X clock is also generated by the serializer and
transmitted by the LVDS buffer. The 1X clock (referred to
as ADCLKP/ADCLKN) is used to determine the start of the
12-bit data frame. The sync mode (enabled through a
register setting) gives out a data of six 0s followed by six
1s. Using this mode, the 1X clock can be used to determine
the start of the data frame. In addition to the deskew mode
pattern and the sync pattern, a custom pattern can be
defined by the user and output from the LVDS buffer.
NOISE COUPLING ISSUES
High-speed mixed signals are sensitive to various types of
noise coupling. One of the main sources of noise is the
switching noise from the serializer and the output buffers.
Maximum care is taken to isolate these noise sources from
the sensitive analog blocks. As a starting point, the analog
and digital domains of the chip are clearly demarcated.
AVDD and AVSS are used to denote the supplies for the
analog sections, while LVDD and LVSS are used to denote
the digital supplies. Care is taken to ensure that there is
minimal interaction between the supply sets within the
device. The extent of noise coupled and transmitted from
the digital to the analog sections depends on the following:
1. The effective inductances of each of the supply/ground
sets.
2. The isolation between the digital and analog
supply/ground sets.
Smaller effective inductance of the supply/ground pins
leads to better suppression of the noise. For this reason,
multiple pins are used to drive each supply/ground. It is
also critical to ensure that the impedances of the supply
and ground lines on board are kept to the minimum
possible values. Use of ground planes in the board as well
as large decoupling capacitors between the supply and
ground lines are necessary to get the best possible SNR
from the device.
It is recommended that the isolation be maintained on
board by using separate supplies to drive AVDD and
LVDD, as well as separate ground planes for AVSS and
LVSS.
The use of LVDS buffers reduces the injected noise
considerably, compared to CMOS buffers. The current in
the LVDS buffer is independent of the direction of
switching. Also, the low output swing as well as the
differential nature of the LVDS buffer results in low-noise
coupling.

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